Ben Eater's SAP came from "Digital Computer Electronics" by Albert Paul Malvino and Jerald A. Brown https://en.wikipedia.org/wiki/Simple-As-Possible_computer
Yep this is how I built my SAP 20 years ago.
Show HN: We built an 8-bit CPU as 2nd year EE students
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Re: Show HN: We built an 8-bit CPU as 2nd year EE students
#12With all the talk about developers being lazy and younger folk not understanding the technology they use, it is always great to see examples of core foundational work still being done. Makes the rest of that talk feel like fear mongering.
I did an undergraduate electrical engineering degree some years ago. Building a CPU much like this one was the final project in our second digital design class. The difference here from the usual approach, as they point out, is that this is a gate-by-gate design you could assemble out of 74-series logic gates on a breadboard rather than the more common Verilog/VHDL designs that target FPGAs. Definitely a more tedious, time consuming approach, but I'm not convinced it's more conceptually difficult. By the time you're building a CPU, you've probably already built the component parts like the adders out of pure logic gates, anyway.
Not to say that this is easy, but I think you'd find that a whole lot more people are doing this kind of thing than you might think.
Re: Show HN: We built an 8-bit CPU as 2nd year EE students
#13Neat!
Now do it the other way round and make the 8 bit cpus become a 2nd year EE student.
Re: Show HN: We built an 8-bit CPU as 2nd year EE students
#14[flagged]
Re: Show HN: We built an 8-bit CPU as 2nd year EE students
#15amazing 2nd year i was playing starcraft all day
Re: Show HN: We built an 8-bit CPU as 2nd year EE students
#16Very nice. I wonder if implementing a one-instruction set computer (for example something that implements Adrian Cable's subleq VM, see https://www.ioccc.org/2025/cable/) would be educational and whether it can make the design of a computer from discrete logic chips simpler or more complex. Though it would very likely not be as efficient.
Re: Show HN: We built an 8-bit CPU as 2nd year EE students
#17Logisim was the shit back in Uni
Very implressive tbh
You should include a screenshot of the logisim diagram
Re: Show HN: We built an 8-bit CPU as 2nd year EE students
#18That ipc lol were all 8bit CPUs less than1 instruction per cycle?
Re: Show HN: We built an 8-bit CPU as 2nd year EE students
#19This is also very well documented. Probably as part of the assessment, but it's nice to see.
It doesn't appear to have any kind of interrupts, which is quite a limitation for actual usecases, but also makes the architecture much simpler.
The use of dual phase clocking is interesting. The document describes it as having the control and data paths operating on opposite phases. I'm curious as to where you got this technique from, since it's not common (apart from the use of both edges by DDR RAM). I also suspect that it would go away if you had better tooling for managing setup and hold violations (does logisim do that for you, or did you have to manage it manually somehow?). Not all FPGA tools like nonstandard clock architectures.
Re: Show HN: We built an 8-bit CPU as 2nd year EE students
#20This is also very well documented. Probably as part of the assessment, but it's nice to see. It doesn't appear to have any kind of interrupts, which is quite a limitation for actual usecases, but also makes the architecture much simpler. The use of dual phase clocking is interesting. The document describes it as having the control and data paths operating on opposite phases. I'm curious as to where you got this techn…
The dual phase clocking is perhaps inspired by the 6502.