You should check out GreenArrays. Their G144A12 is an amazing little asynchronous chip. It's not an FPGA though.
Ask HN: Asynchronous FPGAs and flowchart programming
41–50 of 57 posts
Re: Ask HN: Asynchronous FPGAs and flowchart programming
#42Not sure if you are actually talking about clockless logic. Maybe you are talking about asynchrony at a higher level of granularity. But in fact there was a company founded to make FPGAs based on clockless logic: Achronix. They found that their customers wanted to map clocked designes onto their FPGAs and don't make any noise about clockless anymore - possibly their designs still use it under the hood, possibly not.
Yes clockless logic no handshaking
What handshaking? Never heard of that before.
Re: Ask HN: Asynchronous FPGAs and flowchart programming
#43Earlier quoted context omitted.
There are some advantages. For example, in Alpha AXP they measured that 60% of energy spent in device is due to clock propagation. No clocks to tick - no energy spent. Why do we need to even clock FPU? Or bus - if we are in loop that is in cache. Another example: in async design ripple-carry adder will exhibit O(log(N)) expected time, with worst case being O(N) and most of the time it will be even less O(log(L)) wher…
Another advantage is higher yield due to higher tolerance to the production defects.
This implies yield loss is mostly due to small delay defects and not stuck-at faults. Are you sure this is the case?
Re: Ask HN: Asynchronous FPGAs and flowchart programming
#44"Fastest way to compute" This isn't necessarily true, especially considering the architecture of an FPGA. You have no control over the routing of the circuit and you're extremely restricted by the tools (which have decades of work towards synchronous circuits). More often than not, a synchronous circuit will end up being faster and more practical (there's a lot of overhead for async as well). Another issue is that a…
There's a lot of interesting research out there as designers having been toying with asynchronous for decades.
For example this one sponsored by Intel where they put an asynchronous instruction length decoder into a Pentium.
https://my.eng.utah.edu/~kstevens/docs/rappid.pdf
They won on latency and power with comparable area. The issue that blocked it was DFT CAD and the ATE infrastructure doesn't exist for asynchronous designs.
Re: Ask HN: Asynchronous FPGAs and flowchart programming
#45Earlier quoted context omitted.
No clocks to tick - no energy spent If only it were that simple. Logic gates take time to settle, and each input gate switch or transient will have a ripple effect on all its downstream gates, which can be many in a complex circuit. Synchronous logic elements such as latches will block the spurious transients from propagating beyond the next clock barrier, but if you lack those, you also lose the protection against p…
Contemporary intermodule designs are pipelined and message-oriented exactly because it is hard to predict difference in signal path length for long paths. I am talking about high speed buses from ARM, I think I read about them in 2016 or so. The same can be done with asynchronous designs, in more relaxed way. You said that asynchronous designs are less predictable in their use of power. Can you elaborate on that?
> The same can be done with asynchronous designs, in more relaxed way.
Sure, just ask these guys:
https://chronostech.com/technology
Chronos Link: A QDI Interconnect for Modern SoCs https://ieeexplore.ieee.org/document/9179196
It's compatible with TileLink, which is SiFive's Fabric. https://bar.eecs.berkeley.edu/projects/tilelink.html
Re: Ask HN: Asynchronous FPGAs and flowchart programming
#46Not sure if you are actually talking about clockless logic. Maybe you are talking about asynchrony at a higher level of granularity. But in fact there was a company founded to make FPGAs based on clockless logic: Achronix. They found that their customers wanted to map clocked designes onto their FPGAs and don't make any noise about clockless anymore - possibly their designs still use it under the hood, possibly not.
Yes clockless logic no handshaking
Even the most trivial design will need some form of synchronization which implies handshaking of some kind.
Asynchronous design is a really interesting field where it's pretty easy to get wins at the circuit level, but it's much harder to win at the system level. Especially when you realize there is no rule that says the system needs only one clock domain, and the period of those domains doesn't actually have to be constant.
I highly recommend you spend some time with a recent overview in the field if you're serious about it. Here is a good one:
http://www.cs.columbia.edu/~nowick/nowick-singh-async-IEEE-D...
Re: Ask HN: Asynchronous FPGAs and flowchart programming
#47Looks like you want to implement "asynchronous circuit": https://en.wikipedia.org/wiki/Asynchronous_circuit These basically need a handshaking logic for every independent data path.
Take a look at the you know solutions patent. It doesn't use handshaking and the design can be clockless. https://www.freepatentsonline.com/10181003.html
The main issue with the comments are people are mixing terms without knowing it.
To many a single instruction executed on a CPU is an atomic event. This is not the case for a circuit designer (and FPGAs are closer to circuit design as technically what you're doing is configuring them) For us an instruction on a CPU is a sequence of many smaller events, sometimes happening in parallel, which all need to be properly ordered to get a correct result. The most basic example is adding two multi-bit numbers, as was given in tremon's earlier comment, how does the next circuit know that all the bits in the result are ready to be consumed? To us those are parallel processes too, and we synchronize them. Sometimes by design (i.e. this process is guaranteed to complete before the next tick) and sometimes with a separate handshaking circuit. But no matter what, there is always some form of synchronization present in the machine itself.
Re: Ask HN: Asynchronous FPGAs and flowchart programming
#48I know of people who build a microprocessor in SimuLink.
Re: Ask HN: Asynchronous FPGAs and flowchart programming
#49Earlier quoted context omitted.
Take a look at the you know solutions patent. It doesn't use handshaking and the design can be clockless. https://www.freepatentsonline.com/10181003.html
The main issue with the comments are people are mixing terms without knowing it. To many a single instruction executed on a CPU is an atomic event. This is not the case for a circuit designer (and FPGAs are closer to circuit design as technically what you're doing is configuring them) For us an instruction on a CPU is a sequence of many smaller events, sometimes happening in parallel, which all need to be properly or…
If you step back and look at a flowchart or thousands of flowcharts that represent parallel tasks, I think the object of the patent is to get those flowcharts to propagate (i.e. execute on their own) without a processor. The propagation flow is always forward (not requiring a handshake) until a loopback is reached on the flowchart. A new propagation begins at the loopback destination block. The new propagation flow may or may not follow the same flowchart past depending on decision events. Synchronization takes place at the flowchart level and not at the circuit level. To synchronize, one flowchart sets a variable and other flowcharts can test the variable and decide what to do. The flowcharts are the code which synthesize directly to action, test and task objects without Boolean or state machine structures. These structures (circuits) are synchronous when the flowcharts are implemented in a standard FPGA but the flowcharts themselves remain asynchronous. The patent mentions an FPFA (field programmable flowchart array) that would use clock less circuitry.
Re: Ask HN: Asynchronous FPGAs and flowchart programming
#50Earlier quoted context omitted.
The main issue with the comments are people are mixing terms without knowing it. To many a single instruction executed on a CPU is an atomic event. This is not the case for a circuit designer (and FPGAs are closer to circuit design as technically what you're doing is configuring them) For us an instruction on a CPU is a sequence of many smaller events, sometimes happening in parallel, which all need to be properly or…
If you step back and look at a flowchart or thousands of flowcharts that represent parallel tasks, I think the object of the patent is to get those flowcharts to propagate (i.e. execute on their own) without a processor. The propagation flow is always forward (not requiring a handshake) until a loopback is reached on the flowchart. A new propagation begins at the loopback destination block. The new propagation flow m…
Is the flowchart system different from a transition system? https://en.wikipedia.org/wiki/Transition_system
If not, I don't know of a way to make that machine without some timing assumptions. https://authors.library.caltech.edu/26721/2/postscript.pdf
Maybe other people do though...