Ask HN: Where do I get started on ASICs, FPGA, RTL, Verilog et. al? • Hacker News Board

Re: Ask HN: Where do I get started on ASICs, FPGA, RTL, Verilog et. al?

#111

Post by Gracana » Mon, Oct 02, 2017, 2:39 PM UTC

lvoudour wrote: post #42

KSteffensen wrote: post #13

Earlier quoted context omitted.

If you're worried about vendor lock-in, FPGA/ASIC design is not for you. The design tool market is horrible. That said, for a novice there are no significant differences in features between Altera and Xilinx. The place where you might see problems is mostly in simulation, where the big three tool vendors support different language features in SystemVerilog and VHDL-2008. Again, this is not likely to be a problem for…

>The design tool market is horrible I wouldn't say it's horrible, it's just not open source (mainly because it's mostly a high-end market). You can easily get by with the free versions of the implementation/simulation tools if you're a hobbyist

It's not really a market, though. If you have decided to use Xilinx FPGAs, you're going to use Xilinx tooling. Period.

For someone coming from software programming, that seems very strange. But you get over it.

Re: Ask HN: Where do I get started on ASICs, FPGA, RTL, Verilog et. al?

#112

Post by sandGorgon » Mon, Oct 02, 2017, 3:25 PM UTC

deepnotderp wrote: post #85

sandGorgon wrote: post #35

Its quite late here, so I'll be brief. You mentioned the words "how IP is managed in chip industry" - so I'm going to move past the bookish knowledge and the tutorials and the open source code. The chip design and EDA industry are very closeted and niche - there is so much knowledge there that is not part of any manual. For example for a newcomer, you wouldn't even know what testing and validation in chip design woul…

While I agree that the semiconductor industry is crushingly conservative, it's not necessarily that bad. You can still use many of the "old classics", you just have to remember that instead of 10 design rules there are 10K ;) In all honesty though, a significant amount of the complexity can be hidden in the eda layers nowadays, and instead of dealing with the er,"tenacious"- synthesis tools, you can use good alternat…

Is that actually viable ? The Synopsy and Cadence tools have had several million man hours put into it.

Does something like Chisel give you competitive apples-to-apples performance ? All the way to GDS?

Re: Ask HN: Where do I get started on ASICs, FPGA, RTL, Verilog et. al?

#113

Post by TomVDB » Mon, Oct 02, 2017, 4:18 PM UTC

gluggymug wrote: post #99

spear wrote: post #82

Earlier quoted context omitted.

That's a false dichotomy -- you can do FPGA verification in addition to simulation-based verification. And yes, there are ASIC teams that have successfully done that.

At the SoC level, I don't think so. The reasons are numerous. I already gave a few. I will give another. Once you have to integrate hard IP from other parties, you cannot synthesise it to FPGA. Which means you won't be able to run any FPGA verification with that IP in the design. You can get a behavioural model that works in simulation only. In fact it is usually a requirement for Hard IP to be delivered with a cycle…

As another veteran in the ASIC industry: we are using FPGAs to verify billion transistor SOCs before taping out, using PCBs that have 20 or more of the largest Xilinx or Altera FPGAs.

It's almost pointless to make the FPGA run the same tests as in simulation. What you really want is to run things that you could never run in simulation. For example: boot up the SOC until you see an Android login screen on your LCD panel.

A chip will simply not tape out before these kind of milestones have been met, and, yes, bugs have been found and fixed by doing this.

The hard macro IP 'problem' can be solved by using an FPGA equivalent. Who cares that, say, a memory controller isn't 100% cycle accurate? It's not as if that makes it any less useful in feeding the units that simply need data.

Re: Ask HN: Where do I get started on ASICs, FPGA, RTL, Verilog et. al?

#114

Post by zerohp » Tue, Oct 03, 2017, 5:10 PM UTC

scott_wilson46 wrote: post #104

gluggymug wrote: post #41

As a veteran from the chip industry, I should warn you that all these suggestions about FPGAs for prototyping are not really done that much in the ASIC industry. The skills to do front end work are similar but an ASIC design flow generally doesn't use an FPGA to prototype. They are considered slow to work with and not cost effective. IP cores in ASICs come in a range of formats. "Soft IP" means the IP is not physical…

I've had a different experience to this. I've worked on ASIC's for over ten years and have had experience with nearly all aspects of the design flow (from RTL all the way to GDS2 at one point or another). I've taped out probably 20+ chips (although I've been concentrating on FPGA's for the last three years). Every chip that I've taped out has had extensive FPGA prototyping done on the design. This is in a variety of…

My experience agrees with yours. Many big-budget teams use a hardware emulator like the Palladium XP or the similar Synopsis device. Both built from FPGAs.

Hardware emulators are expensive, but a single mask respin at 7, 10, or 16nm is even more expensive.

Re: Ask HN: Where do I get started on ASICs, FPGA, RTL, Verilog et. al?

#115

Post by gluggymug » Tue, Oct 03, 2017, 11:43 PM UTC

zerohp wrote: post #114

scott_wilson46 wrote: post #104

Earlier quoted context omitted.

I've had a different experience to this. I've worked on ASIC's for over ten years and have had experience with nearly all aspects of the design flow (from RTL all the way to GDS2 at one point or another). I've taped out probably 20+ chips (although I've been concentrating on FPGA's for the last three years). Every chip that I've taped out has had extensive FPGA prototyping done on the design. This is in a variety of…

My experience agrees with yours. Many big-budget teams use a hardware emulator like the Palladium XP or the similar Synopsis device. Both built from FPGAs. Hardware emulators are expensive, but a single mask respin at 7, 10, or 16nm is even more expensive.

There is a distinction between hardware emulators and FPGAs. Though hardware emulators such as Palladiums may use FPGAs inside them they don't work the same way in terms of validation. The two tools are very different to use.

See myth 7 here: http://www.electronicdesign.com/eda/11-myths-about-hardware-...