Show HN: A tiny LLM running at 21,000 tok/s on a $250 FPGA (Live Demo)
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Re: Show HN: A tiny LLM running at 21,000 tok/s on a $250 FPGA (Live Demo)
#2Re: Show HN: A tiny LLM running at 21,000 tok/s on a $250 FPGA (Live Demo)
#3Re: Show HN: A tiny LLM running at 21,000 tok/s on a $250 FPGA (Live Demo)
#4Re: Show HN: A tiny LLM running at 21,000 tok/s on a $250 FPGA (Live Demo)
#5I didn't expect the 2,000 connection sweep to stay flat, since all of them are sharing one stream. What does per user latency look like at that end of the sweep?
The benchmark sweep is 2,000 concurrent active requesters hammering it constantly, real traffic is mostly lurkers, which cost a file descriptor and nothing else. the interactive feel actually gives out earlier than the queue math. The speculative-typing UI wants sub-second replies, and that budget blows around 100–150 simultaneous typists.
I've been logging the stats since it went live, unfortunately it didn't hit FP. Peak was 10 concurrent connections (13 uniques in the busiest half hour), ~580 requests and ~37k tokens served, and at no point did two people actually have an inference in flight at the same moment which would have been the real test for the queue, every visitor got the fabric to themselves, p50 ~23ms. so the 2,000-conn drill was not stressed today. the one blemish: a single window with p95 ~57s, which lines up with the model-rotation FPGA reconfigure rather than load. A request that arrives mid-reflash waits out the ~25s swap. if this thread sends 50× more people, the queue math above says it holds.
I need to discard the requests that overlap the model changeover for a truer result.
Re: Show HN: A tiny LLM running at 21,000 tok/s on a $250 FPGA (Live Demo)
#6Sure, you can go ASIC and go even faster, but the thing around GPU is that they scale well for both training and inference, and the technical floor is low.
The level to get into FPGA design is insanely high, you've got to read timing diagrams, you need to know combinatorial and sequential logics and good sense of boolean algebra, you need to have an asynchronous signal based mindset which is vastly different from CPU/GPU, you need to know netlist and you need to endure the time it takes for the EDA to finish generating it. Yosys is still years behind Xilinx
There is a reason GPUs are called accelerators; it sacrifices and does not try to really specialize on one particular thing, except high parallel dataflow and branch-free calculation. Otherwise we will all be using DSPs
Re: Show HN: A tiny LLM running at 21,000 tok/s on a $250 FPGA (Live Demo)
#7But the problem is not that your model is fast. Sure, you can go ASIC and go even faster, but the thing around GPU is that they scale well for both training and inference, and the technical floor is low. The level to get into FPGA design is insanely high, you've got to read timing diagrams, you need to know combinatorial and sequential logics and good sense of boolean algebra, you need to have an asynchronous signal…
Re: Show HN: A tiny LLM running at 21,000 tok/s on a $250 FPGA (Live Demo)
#8Any article, even the really good ones on HN, while they get positive comments, for whatever reason, always get a lot of negative ones, too...
That is, the negative comments are absolutely unavoidable, even for people accomplishing great things!
I personally think that what you've done is brilliant, absolutely brilliant!
I can't wait to see more in this space...
Brilliant, absolutely brilliant!
Re: Show HN: A tiny LLM running at 21,000 tok/s on a $250 FPGA (Live Demo)
#9Ignore the naysayers! Any article, even the really good ones on HN, while they get positive comments, for whatever reason, always get a lot of negative ones, too... That is, the negative comments are absolutely unavoidable, even for people accomplishing great things! I personally think that what you've done is brilliant, absolutely brilliant! I can't wait to see more in this space... Brilliant, absolutely brilliant!