Show HN: A Project Oberon System version running on RISC-V instead of RISC-5
1–10 of 21 posts
Re: Show HN: A Project Oberon System version running on RISC-V instead of RISC-5
#2> The whole system runs on a low-cost development board (Xilinx Spartan-3 by Digilent, with 1 MB of static RAM)
If somebody wants their FPGA work to be available, they better choose MiSTer FPGA from the beginning. Costlier, but way more likely to be found around.
Re: Show HN: A Project Oberon System version running on RISC-V instead of RISC-5
#3> The whole system runs on a low-cost development board (Xilinx Spartan-3 by Digilent, with 1 MB of static RAM) If somebody wants their FPGA work to be available, they better choose MiSTer FPGA from the beginning. Costlier, but way more likely to be found around.
The availability of the board to run Wirt's system was an issue pretty soon. There were even people who offered their own boards to fill the gap (e.g. https://web.archive.org/web/20160831063355/http://oberonstat...).
My system version instead runs on RISC-V, so no custom FPGA implementation, currently on an emulator, but eventually on the ESP32 (which has a much better availability).
Re: Show HN: A Project Oberon System version running on RISC-V instead of RISC-5
#4> The whole system runs on a low-cost development board (Xilinx Spartan-3 by Digilent, with 1 MB of static RAM) If somebody wants their FPGA work to be available, they better choose MiSTer FPGA from the beginning. Costlier, but way more likely to be found around.
> they better choose MiSTer FPGA from the beginning.
Well, the MiSTer project was yet 4 years from being launched back in 2013 when the RISC-5 was implemented in FPGA, so I hope you'd excuse Wirth from not choosing it.
Re: Show HN: A Project Oberon System version running on RISC-V instead of RISC-5
#5Would it be practical to have the ESP P4 self-host?
Re: Show HN: A Project Oberon System version running on RISC-V instead of RISC-5
#6Would it be practical to have the ESP P4 self-host?
The ESP32-P4 is actually my target platform. I have a cross-compiler toolchain based on my own OP2 compiler version (see https://github.com/rochus-keller/op2/) which makes it easier to migrate. The Project Oberon System is an "intermezzo" for my actual goal, the Oberon System 3; the latter can also run my OP2 version and would thus be able to self-host. I didn't try yet to run OP2 under the Project Oberon System, but with some patience I assume it is feasible.
Re: Show HN: A Project Oberon System version running on RISC-V instead of RISC-5
#7> The whole system runs on a low-cost development board (Xilinx Spartan-3 by Digilent, with 1 MB of static RAM) If somebody wants their FPGA work to be available, they better choose MiSTer FPGA from the beginning. Costlier, but way more likely to be found around.
> they better choose MiSTer FPGA from the beginning. Well, the MiSTer project was yet 4 years from being launched back in 2013 when the RISC-5 was implemented in FPGA, so I hope you'd excuse Wirth from not choosing it.
And shortly after Wirth launched his RISC-5 system, the original FPGA board went out of production.
Re: Show HN: A Project Oberon System version running on RISC-V instead of RISC-5
#8Would it be practical to have the ESP P4 self-host?
The ESP32-P4 is actually my target platform. I have a cross-compiler toolchain based on my own OP2 compiler version (see https://github.com/rochus-keller/op2/ ) which makes it easier to migrate. The Project Oberon System is an "intermezzo" for my actual goal, the Oberon System 3; the latter can also run my OP2 version and would thus be able to self-host. I didn't try yet to run OP2 under the Project Oberon System, bu…
This is super interesting Rochus. Are you targeting Oberon System 3 in particular because it adds tcp/ip networking support? In my opinion that would make it a much more interesting system to kick the tires on, if so!
Re: Show HN: A Project Oberon System version running on RISC-V instead of RISC-5
#9Earlier quoted context omitted.
> they better choose MiSTer FPGA from the beginning. Well, the MiSTer project was yet 4 years from being launched back in 2013 when the RISC-5 was implemented in FPGA, so I hope you'd excuse Wirth from not choosing it.
And shortly after Wirth launched his RISC-5 system, the original FPGA board went out of production.
Which most likely wasn't predictable for him.
FPGAs were never that maker friendly, due to the whole ecosystem.
Re: Show HN: A Project Oberon System version running on RISC-V instead of RISC-5
#10Love your commitment to this. You are doing excellent work to keep Wirth's computing spirit alive. Oberon's philosophy ( https://people.inf.ethz.ch/wirth/Oberon/Oberon07.Report.pdf ) is beautiful for the power it hides behind its simplicity and I wish it was a more popular language ...