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Show HN: A Project Oberon System version running on RISC-V instead of RISC-5

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Re: Show HN: A Project Oberon System version running on RISC-V instead of RISC-5

#11

Post by Rochus »

berkeleynerd wrote: post #8
Rochus wrote: post #6

Earlier quoted context omitted.

The ESP32-P4 is actually my target platform. I have a cross-compiler toolchain based on my own OP2 compiler version (see https://github.com/rochus-keller/op2/ ) which makes it easier to migrate. The Project Oberon System is an "intermezzo" for my actual goal, the Oberon System 3; the latter can also run my OP2 version and would thus be able to self-host. I didn't try yet to run OP2 under the Project Oberon System, bu…

This is super interesting Rochus. Are you targeting Oberon System 3 in particular because it adds tcp/ip networking support? In my opinion that would make it a much more interesting system to kick the tires on, if so!

Thanks. I rather do it as a "proof of concept" to demonstrate that the Oberon System is a (hopefully) great fit with today's microcontroller boards, particularly the Olimex ESP32-P4-PC, which even has a HDMI connector. I already migrated the system to the Raspi Zero 2 which is yet another lean target, but actually oversized for the Oberon System, which doesn't even require an MMU (not to mention multiple cores). The networking support code is currently not used, because it would require yet another (pretty complex) driver. But it might be feasible (with a lot of patience) to implement it directly on the board as soon as the system and compiler run stable on it.

Re: Show HN: A Project Oberon System version running on RISC-V instead of RISC-5

#12

Post by cxr »

Readers encountering this project for the first time should be aware that the earlier Oberon-on-RISC-V project https://github.com/solbjorg/oberon-riscv> (HN discussion: https://news.ycombinator.com/item?id=25497002>) exists and was already discussed on the mailing list:

https://lists.inf.ethz.ch/pipermail/oberon/2026/017161.html>

Re: Show HN: A Project Oberon System version running on RISC-V instead of RISC-5

#13

Post by Rochus »

thisislife2 wrote: post #10

Love your commitment to this. You are doing excellent work to keep Wirth's computing spirit alive. Oberon's philosophy ( https://people.inf.ethz.ch/wirth/Oberon/Oberon07.Report.pdf ) is beautiful for the power it hides behind its simplicity and I wish it was a more popular language ...

Thanks. Though I migrated the code from Oberon-07 to Oberon 90 (so I could compile it with my OP2 version) and currently I even migrate it to my forthcoming Micron language. The Project Oberon System is very well suited for these kinds of experiments.

Re: Show HN: A Project Oberon System version running on RISC-V instead of RISC-5

#14

Post by butvacuum »

pjmlp wrote: post #9
Rochus wrote: post #7

Earlier quoted context omitted.

And shortly after Wirth launched his RISC-5 system, the original FPGA board went out of production.

Which most likely wasn't predictable for him. FPGAs were never that maker friendly, due to the whole ecosystem.

It probably was NRND on mouser/digikey by then... not that there was much choice in 2013- you went with what you had instead of $1000+ dev boards.

Re: Show HN: A Project Oberon System version running on RISC-V instead of RISC-5

#18

Post by Rochus »

cxr wrote: post #12

Readers encountering this project for the first time should be aware that the earlier Oberon-on-RISC-V project https://github.com/solbjorg/oberon-riscv > (HN discussion: https://news.ycombinator.com/item?id=25497002 >) exists and was already discussed on the mailing list: https://lists.inf.ethz.ch/pipermail/oberon/2026/017161.html >

People unaware of Project Oberon should rather have a look at https://projectoberon.net/ where they can find the free book and additional material by Prof. Wirth.

Re: Show HN: A Project Oberon System version running on RISC-V instead of RISC-5

#19

Post by OCTAGRAM »

Joker_vD wrote: post #4
OCTAGRAM wrote: post #2

> The whole system runs on a low-cost development board (Xilinx Spartan-3 by Digilent, with 1 MB of static RAM) If somebody wants their FPGA work to be available, they better choose MiSTer FPGA from the beginning. Costlier, but way more likely to be found around.

> they better choose MiSTer FPGA from the beginning. Well, the MiSTer project was yet 4 years from being launched back in 2013 when the RISC-5 was implemented in FPGA, so I hope you'd excuse Wirth from not choosing it.

Indeed, I excuse

Re: Show HN: A Project Oberon System version running on RISC-V instead of RISC-5

#20

Post by OCTAGRAM »

Rochus wrote: post #3
OCTAGRAM wrote: post #2

> The whole system runs on a low-cost development board (Xilinx Spartan-3 by Digilent, with 1 MB of static RAM) If somebody wants their FPGA work to be available, they better choose MiSTer FPGA from the beginning. Costlier, but way more likely to be found around.

The availability of the board to run Wirt's system was an issue pretty soon. There were even people who offered their own boards to fill the gap (e.g. https://web.archive.org/web/20160831063355/http://oberonstat... ). My system version instead runs on RISC-V, so no custom FPGA implementation, currently on an emulator, but eventually on the ESP32 (which has a much better availability).

What do you think about ClockworkPi uConsole Kit R-01, ClockworkPi DevTerm Kit R-01, OrangePi?
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