Viewing profile — xw3089

There are tons of other practical problems. The HLS generated verilog is name mangled. This makes it really hard to generate all the various control files you need to run the EDA f…

I think this comes from the idea that running the EDA flow is like compiling software and that’s the problem, it’s not. The EDA flow, the software that goes from verilog to manufac…

You’re preaching to the choir on improving validation. Like you mentioned, In commercial designs that’s where a majority of the man hours actually go, and coincidentally where basi…

Maybe not no one https://berkeley.municipal.codes/BMC/12.90.050

Yes, that happened to my car. But one could still drive their car after the failure and there was a free recall. https://www.tesla.com/support/8gb-emmc-recall-frequently-ask...

Genuinely curious, what’s the argument for locking down the FPGA?