Viewing profile — xpuente

But how can you verify that the processor's own software, which ultimately runs the application, has not been compromised?

How can you have a secure enclave without hardware attestation? Processor root-key is the source for all.

There are also many high-performance Chinese implementations that are open-source (e.g., XuanTie C910, XiangShan, etc.). While achieving an open-core design comparable to Zen 5 is …

No: RISC is open ARM is closed. I suspect that many projects—such as BOOM—have stalled as a consequence of this situation. If it continues, the long-term impact will be highly detr…

Desperate to run without even knowing how to walk.

This is going to end badly — and soon. It’s ironic that catastrophic forgetting (i.e., the inability to perform continuous learning) and hallucinations (i.e., the failure to recogn…

Konrad had the ideas; others received the glory. History has been unfair to him—he was simply on the wrong side of it.

Consciousness, once engineered, will make any biology redundant.

It won’t be us. It will be our descendants — the machines.

AGI may finally arrive — the long-awaited gold transmutation dreamt of by modern "linear algebra" alchemists.

As far as I know, pruning is related to age. At birth, we have a massive number of silent synapses. As we grow older, those that remain unused (i.e., inactive) tend to disappear. T…

The issue is that no one fully understands why synaptic pruning occurs in biology. Large language models have no direct connection to biological systems, and pruning in LLMs is no …

The usefulness of AST is not limited to biological systems. A hypothetical conscious electronic system might also need AST to: (1) stabilize internal states more quickly during lea…

Secure enclaves can solve the problem once for all. I don't understand why is not applied (given the support in current hardware).

"Heavier-than-air flying machines are impossible.", -- 1895, Lord Kelvin, president of the Royal Society

Proof of that this is wrong, is that our brains require <20W of power. Non-brute force AI will be very efficient. Simple operations (int add/cmp) and no float matrix multiplication…

My comment was not about the ISA implementation or specification, It's about the TCB (trusted compute base), which in Apple (like intel and AMD) is closed. In RiscV is open. I woul…

It has to with the secure processor. Although you seems to ignore what is the TCB.

Security through obscurity is really a bad idea, and Apple is no exception. In the long run, this will likely drive the adoption of RiscV as a better alternative.

I wonder what will happen if someone figures out that fused FP mult add is no longer needed (e.g. just count spikes and add subtract permanence). This could be a big problem for th…

Most likely related to this: https://www.searchenginejournal.com/openai-pauses-new-chatgp... The back-end cost does not scale. Hence, they have a big problem. AGI nonsense reasons …

We need RISCV hardware with Ztso extension to shine here. Enforcing Total store ordering (TSO) over a release consistency (RC) memory model is otherwise a pain. I don't know if Dyn…