Viewing profile — xoranth

> Crappy Pixel Fold 2022 mid-range Android CPU Can you share what LLMs do you run on such small devices/what user case they address? (Not a rhetorical question, it's just that I se…

Are there any good how-tos for how to set up a non-trivial container with s6 and s6-rc? Last time I looked at this the documentation was pretty sparse, and more of a reference and …

I believe they mean that since it bypasses the (Tokio) scheduler, so if you use it in async code you lose the main benefit of async code (namely, the scheduler is able to switch to…

On Linux, you might be able to use userfaultfd to make it async...

Thank you for your reply! > GPUs are also just generally a lot more limiting than SIMD in many other ways. What do you mean? (besides things like CUDA being available only on Nvidi…

Sure, but how well do they perform compared to vector loads? Do they get converted to vector load + shuffle uops, and therefore require a specific layout anyway? Last time I tried …

General questions for gamedevs here. How useful is SIMD given that now we have compute shaders on the GPU? If so, what workloads still require SIMD/why would you choose one over th…

On x86-64, compilers use SIMD instructions and registers to implement floating point math, they just use the single lane instructions. E.g. ( https://godbolt.org/z/94b3r8dMn ): flo…

Sounds a bit like Google's proposal for a `switchto_switch` syscall [1] that would allow for cooperative multithreading bypassing the scheduler. (the descendants of that proposal i…

Thanks!

Is the extension you wrote public?

How would this interact with `io_uring`, especially the polling modes (IO_SETUP_SQPOLL, IO_SETUP_IOPOLL)?

I believe the reason they offer no details about how they tuned the kernels is that the tuning is done by a tool provided by AMD. See here: https://rocm.docs.amd.com/projects/rocBL…

Is there any good article on NT internals (that isn't Russinovich' book), that highlight where/how it is better than Linux and other *BSDs? When asked people point to IOCP vs epoll…

> expression templates That's one of the cases where you can't "mechanically" translate C++ to Rust. To obtain the same result, a good choice would be a proc macro. Which is a pain…

Thanks!

> That allows things like individual threads to take locks, which is a pretty big leap. Does anyone know how those get translated into SIMD instructions. Like, how do you do a CAS …

Do you know any good tutorial for ISPC? Documentation is a bit sparse.

It is the same reason in software sometimes you batch operations: When you add two numbers, the GPU needs to do a lot more stuff besides the addition. If you implemented SIMT by ha…

I believe the author is referring to how many logical threads/hyperthreads can a core run (for AMD and Intel, two. I believe POWER can do 8, Sparc 4). The extra physical registers …

People have engineered solutions to make what is available practical (see all the various quantization schemes that have come out). It is just that there's a limit to how much you …

Location: Europe, CET timezone Remote: Yes Willing to relocate: Yes (EU/Switzerland) Technologies: C++, Python, Rust, Numpy, Pandas, sklearn, numba, SQL, Rust, Assembly. Résumé/CV:…

Thanks for the clarification!

I believe something like the mechanism you are describing has been in production at Google for at least a decade. See this talk [1]. The kernel interface that the article uses (cal…