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One of my worry about the presented ideas, and this is present in RISC-V vector ISA if I'm not mistaken, is that register-size-independent vector instructions have random execution…

An old attempt to this was SWAR-C, (SIMD within a register - C), that could target Neon, altivec and MMX/SSE. I think SWAR-C nailed the syntax (a vector ?: operator, for example). …

As pointed out: it's done, look for algorithmics over grammar-based compression. Querying and search is one of the operation that is doable on compressed data. See Algorithmics on …

I'd say there are some possibilities in compression formats that are transparent to certain operations, that is compressed data you can process as is (without decompressing). For e…

A few years ago, before the advent of Copilot (and ChatGPT), I was telling my students their future as programmer was bleak, because most coding is either interfacing stuff, or cre…