Viewing profile — shetaye

I assume the idea is to have the entire constellation be the data center in question. Laser back haul transceiver bandwidth is in the same order of magnitude of rack-to-rack bandwi…

Interesting, the protocol seems to assume symmetrical performance i.e. X-...->Y and Y-...->X will have the same latency so long as they follow the same path?

Very interesting! Nice work on your thesis. I am curious: if the data is not resident on the GPU (e.g. multi-TB datasets, line-rate packet inspection, etc.), is this approached bot…

The CPU baseline seems to be the beefy host CPU. The AIE is presumably faster than what you could do with the FPGA (DPS, LUT, etc.) alone.

There also exists cuda-gdb[1], a first-party GDB for NVIDIA's CUDA. I've found it to be pretty good. Since CUDA uses a threading model, it works well with the GDB thread ergonomics…

True, but unfortunately the response from Stanford has been to introduce triple and quad rooms ;) This is not entirely their fault. Stanford is subject to Santa Clara County buildi…

I agree in that freshmen should get the "experience" at least once. However, the way Stanford has arranged housing has meant that a good number of students will not live in a singl…

Regarding Stanford specifically, I did not see the number broken down by academic or residential disability (in the underlying Atlantic article). This is relevant, because > Some s…

Great read! I'm sure expensive enterprise tooling exists for busy kitchens to manage safety protocols (or not?), so it is very cool to see high quality tooling for this kind of thi…

Agreed! The gulf between pure-C++ CUDA and PTX is getting larger with these optimizations. My understanding is that Deepseek used PTX instructions that either had no corresponding …

Arguably the OS includes the entire distribution, not just the kernel. MacOS ships the window server and the entire graphics stack, so the GUI is certainly part of MacOS, and so at…

If you are still interested in SMP on a 64-bit ARM, we have had some success with virtual memory/cache/peripherals on the Pi Zero 2 W

You absolutely can, and should! :)

There aren't any 1hr+ lectures, just some readings (selected from the manuals in `docs/`) and a bit of exposition from the professor before diving into the lab. Lots of "as needed"…

IMO this is kind of the tradeoff. In 140E we do touch on virtual memory (w/ coherency handling on our specific ARM core), FAT32 "from scratch", etc. but it comes at the expense of …

People interested in a "read the manual and code it up on real hardware"-type guide should take a look at Stanford's CS140E[1] repo! Students write a bare metal OS for a Raspberry …