Viewing profile — seldridge

> Could even have a crack at toy HDL in the form of the fixed SystemVerilog with a decent type system solution I proposed above using CIRCT as an IR... This is the exact type of ac…

Yes. There's two common types of modules with different behavior here: `Module` and `RawModule`. The former has implicit clock and reset ports. The latter has no implicit clock and…

It gives you a hardware testing environment with system calls for reasonable amounts of wall clock time. If you're simulating actual hardware, e.g., a Verilog description of a RISC…

(Sorry! Just saw this!) Polymorphism makes it way easier to build hardware that can handle any possible data type. Things like queues and arbiters beg for type parameters (you shou…

The MIPS Open ISA project was actually shut down after only a year. [^1] POWER has technically only been "open" for a little under a year. OpenPOWER was always a thing, but this us…

> These are not programming languages, they are hardware definition languages. There's a subtle point in that Verilog/SystemVerilog and VHDL are also just not powerful languages. W…

There is an open PR adding support for the OpenROAD tools [^1]. So, there should be a flow that uses open source VLSI tools eventually. The Google 130nm library is still filling a …

I'm one of the Chisel devs. My biased view is that iterative development with Chisel, to the point of functional verification, is going to be faster than in a traditional RTL langu…

And if this is interesting, Tom gave a great talk at the 2018 Chisel Community Conference on his experiences at that time: https://youtu.be/x_fzoxGpZ_g

Thanks for your question. There are some different design decisions between Chisel and Clash (and one or the other may work better for you!). Chisel is an embedded domain specific …

For non-BRAM/SRAM primitives that you explicitly want to use, your best bet would be a blackbox. However, for memory, Chisel has built in memory hardware types `Mem` (synchronous w…

Thanks for looking into Chisel! Great question! However, this is an incredibly difficult question to answer as it relies on comparing language power. Paul Graham's "Beating the Ave…

One of the Chisel/FIRRTL devs here available to answer any questions. tl;dr: Chisel/FIRRTL is trying to be "LLVM for circuits". Concretely, Chisel is a domain specific language for…

Thanks for taking a look at Chisel and FIRRTL! (Coming from a Chisel/FIRRTL dev...) Couple of clarifying comments: CDE[^1] is really a Rocket Chip[^2] specific design decision mean…

This is a surprisingly difficult concept to express... I've taken a stab at it before on StackOverflow [1]. One angle is that Chisel (or some hardware DSL) gives you the ability to…

If you're interested in playing with Chisel, the "Chisel Bootcamp" is now hosted on Binder meaning you can run through a fair amount of learning content in a browser [1,2]. As a lo…

The author doesn't have this correct. Chisel is a domain specific language for hardware written in Scala that emits Verilog in Chisel2 or an intermediate representation of RTL (FRR…

The really cool thing is that existing implementations of RISC-V microprocessors, like what Berkeley provides, rocket ( https://github.com/ucb-bar/rocket ) and boom ( https://githu…