Viewing profile — scott_wilson46

The ASIC flow is way more involved than the FPGA flow, you need to think about all sorts of other things, like what pads you want on your chip, how you are going to generate clocks…

In my day job as an FPGA developer I am using totally open source tools for simulation and verification (the only tool we pay for is Vivado but you have to pay for that in order to…

I disagree about for loops, you actually end up using these quite a lot in vhdl/verilog (with understanding about what logic you are going to end up with), if you want to do the sa…

I use it exclusively. I know of other trading firms that use verilator too. To be honest, no matter how big the company, how deep the pockets, theres still going to be a finite amo…

I use Icarus Verilog at work for a fairly complex trading system on an FPGA so I disagree that FOSS simulators are almost totally useless. It supports most System Verilog features …

I disagree with this, you don't necessarily need a whole team of people and massive amounts of cash to do FPGA development and you don't necessarily need expensive tools. For my cu…

I've had a different experience to this. I've worked on ASIC's for over ten years and have had experience with nearly all aspects of the design flow (from RTL all the way to GDS2 a…

I think you can treat 60 - 70% of the FPGA design flow as open source. For example, I am developing a system using PCIe, 10G Base T and some logic to send and receive network packe…

In actual fact for Xilinx based FPGA's this is quite straightforward. An example for 10G Base R: You can get Xilinx's component for their pma/pcs for 10g base-r ethernet for free f…

I've heard (although admittedly never seen in practice) that some places take a long time for this sort of things (running over a cluster of computers overnight). If you could do t…

Xilinx provide software drivers and IP for PCIe DMA and memory mapped interfaces. These are fairly easy to integrate (probably not the best for latency though - I've developed my o…

Nowadays, I don't believe you need a paid-for simulator like Questa, VCS, etc. I am developing verilog in my day job for FPGA's using icarus verilog (an open source simulator)which…

Monte Carlo sims for options pricing? I've done this before on FPGA, might have a go at doing it for this instance as a fun exercise to test the concept!

This all seems highly sensible advice to me!

It should be possible to write the majority of the code for an FPGA in a generic fashion and get the tools to infer things like RAM's by the way the Verilog or VHDL is written. Ide…

Actually the IC design tools are a lot more expensive than 50k to 100k. You need a variety of tools for a modern process node (Calibre being one of them usually used for LVS/DRV - …

In fact some of the Stratix 10 FPGAs have over 9 Teraflops...

I think this is a common misconception in the debate about GPU's vs FPGAs. If you take a top of the range GPU you get 2.7 Teraflops of performance (according to the GTP Titan revie…

I think if you can crack the modelling and simulation of asynchronous clock domains then I suspect you will have something that the other HLS solutions don't have at the moment tha…

If you are interested in using python for unit testing there is also Cocotb which is a python based library for running verilog and vhdl simulations. It interfaces to the simulator…

Actually another thing I am curious about is how asynchronous clock domains are handled Usually this is something thats quite tricky to model in a HLS tool. Also, how about simulat…

I can't help but feel that the VHDL that was written is a bit overly verbose. You could probably write something like: i_sm: process(clk, reset) begin if (reset) then state if (dat…

f you are interested. I did something similar for fpga: https://github.com/scottwilson46/FPGARandom

Theres also the SocKit from arrow: http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=E... Very similar to Zynq but from altera rather than xilinx