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Viewing profile — sacheendra

sacheendra

HN member
Joined
Mon, Nov 04, 2013, 3:22 PM UTC
HN karma
764
Public activity
208 items

About sacheendra

s.talluri@vu.nl

Recent public activity

  1. comment
    Comment #42916085

    The authors point out that the PL community values formal methods and hard implementation, but not human factor studies and alternative programming approached like spreadsheets. I'…

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    Comment #38323902

    No satellite was pointed at the path when MH370 was flying.

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    Comment #37403688

    That's only for Gmail, outlook.com, and samsung browser. It is possible to argue that these are not gateways without mental gymnastics. It is fairly easy to migrate out of Gmail an…

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    Comment #36055080

    Storage manufacturers now give the application more control over SSD FTL operations through ZNS. https://zonedstorage.io/docs/introduction/zns . Curious to see how it will be used

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    Comment #35301215

    The project's other github repo is better to learn more about the project: https://github.com/xtofalex/naja The linked repo doesn't have an informative Readme. An example showing s…

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    Comment #27029139

    It is not that surprising. Facebook is complex ecosystem, and therefore experiences lots of outages/problems. Looking at their status page ( https://developers.facebook.com/status/…

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    Comment #26494778

    This I highly unlikely. Hyperscalers like AWS have custom power delivery, rack organization, redundant networking, etc. which make their instances reliable. Long running jobs often…

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    Comment #21683161

    It seems like they plan to do hardware-software co-design. Devices (servers, switches?) and firmware designed specifically for their software stack. A software stack (drivers, OS) …

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    Comment #21636249

    That is not true. The synthesis and layout have to be done separately for the ASIC. That is a more time consuming process than writing verilog code.

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    Comment #21627054

    < 1000 pounds for what is basically license for a livelihood seems cheap.