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ribit

HN member
Joined
Fri, Mar 12, 2021, 3:54 PM UTC
HN karma
1,106
Public activity
302 items

About ribit

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Recent public activity

  1. comment
    Comment #45310648

    Yep. My wife just started as a professor (humanities) and she entered on H1B visa last week, as green card takes years to obtain. I have been offered a teaching job at the same ins…

  2. comment
    Comment #43013282

    Execution with masking is pretty much how broaching works on GPUs. What’s more relevant however is that conditional statements add overhead on terms of additional instructions and …

  3. comment
    Comment #42214304

    Quick note: I looked at the bindless proposal linked from the blog post and their description of Metal is quite outdated. MTLArgumentEncoder has been deprecated for a while now, th…

  4. comment
  5. comment
    Comment #41809116

    M3 GPU uses a new instruction encoding, among other things. Also, it has a new memory partitioning scheme (aka. Dynamic Caching), which probably requires a bunch of changes to both…

  6. comment
    Comment #41807128

    Are you talking about Vulkan or about geometry shaders? The later is simple: because geometry shaders are a badly designed feature that sucks on modern GPUs. Apple has designed Met…

  7. comment
    Comment #41807048

    Apple not supporting Vulkan is a business decision. They wanted a lean and easy to learn API that they can quickly iterate upon, and they want you to optimize for their hardware. V…

  8. comment
    Comment #41117734

    Have you looked at the Swift error model? I really like their design. They use a dedicated try statement to mark call sites that can fail — note that try is not the same as try...c…

  9. comment
    Comment #41112557

    Is this really a new approach? On a cursory look this seems like implicit error propagation with checked exceptions. I am Also curious about authors presentation of the topic. To m…

  10. comment
    Comment #41088192

    While I understand the argument, it would also be good to see some empirical evidence. So far all x86 built need more power to reach the same performance level as ARM. Of course, A…

  11. comment
    Comment #40669606

    > Yes, that my understanding, and that's why I claim it's different from "classical" SIMD I understand, yes, it makes sense. Of course, other architectures can make other optimizat…

  12. comment
    Comment #40657355

    Most NPUs are not directly end-user programmable. The vendor usually provides a custom SDK that allows you to run models created with popular frameworks on their NPUs. Apple is a g…

  13. comment
    Comment #40656944

    > Not sure what you mean by lockstep here. When an operand-collector entry is ready it dispatch it to execute as soon as possible (write arbitration aside) even if other operand-co…

  14. comment
    Comment #40656815

    Modern GPUs are exposing the SIMD behind the SIMT model and heavily investing into SIMD features such as shuffles, votes, and reduces. This leads to an interesting programming mode…

  15. comment
    Comment #40654852

    In an operand-collector architecture the threads are still executed in lockstep. I don't think this makes the basic architecture less "SIMD-y". Operand collectors are a smart way t…

  16. comment
    Comment #40651719

    How would you envision that working at the hardware level? GPUs are massively parallel devises, they need to keep the scheduler and ALU logic as simple and compact as possible. SIM…

  17. comment
    Comment #40650290

    You need to consider this in the context of the relevant task. Nvidia GPUs have extremely high peak performance for GEMM, but when working with LLMs, bandwidth (and RAM capacity) b…

  18. comment
    Comment #40617004

    I remember last year (?) Quancomm proposing an ISA extension that brings ARM-like addressing modes and paired stores to RISC-V, and the community reaction being very negative. Happ…

  19. comment
    Comment #40615947

    I fully support the idea of open instruction sets. I am not as much sold on the idea of cookie-cutter one-size-fits-all instruction sets. RISC-V is very nice for teaching CPU basic…

  20. comment
    Comment #40594710

    Bugs notwithstanding (which I agree are a significant concern for Metal), I'd frankly much prefer to work with a well-designed, streamlined API like Metal instead of a needlesly ve…

  21. comment
    Comment #40501624

    > Note that compact/compress are not actually the key enablers: also with AVX-512 we use table lookups for u64 keys, because this allows us to actually partition a vector and write…

  22. comment
    Comment #40498309

    > Perhaps, though on VQSort it was more like 50% the performance. I looked at the paper and my interpretation is that the performance delta between M1 (Neon) and the Xeon (AVX2) ca…

  23. comment
    Comment #40487931

    > I agree with you we do not only want "very wide SIMD", and it seems to me that 2x512-bit (Intel) or 4x256 (AMD) are actually a good middle ground. I'd already classify this as "v…

  24. comment
    Comment #40481376

    If you do streaming-type operations on long arrays, yes. If your data sizes are small, however, four smaller units might be more flexible. As a naive example, let's take the popula…

  25. comment
    Comment #40481348

    Yes, OoO is expensive — after all, that is the cost of performance. Very wide SIMD is great for energy efficiency if that is what your compute patterns require (there is a good rea…