Viewing profile — pbalcer

This exists in many parts of the world. And is usually reserved for the ultra wealthy, especially if you want it to be near a big city. One famous example is Karuizawa.

Readable code is code that has empathy for the reader and tries to minimize the cognitive load of interpreting it. That's one of the goals of abstraction layers and design patterns…

You'd be surprised how complex a typical memcpy implementation can get to eke out all the performance out of a platform for all the possible scenarios. And while I agree it might n…

SteamOS is a much more streamlined console-like experience for gaming. Even things as simple as system updates is far less annoying on Linux/SteamOS than it is on Windows. This is …

One of the reasons why they can do unified memory efficiently is because the CPU/GPU is a single SoC. If you separate them, you end up with a normal PC architecture, with memory ha…

Disclaimer: I work on this stuff for Intel At least for Intel, that is just not true. Intel's DPC++ is as open as it gets. It implements a Khronos standard (SYCL), most of the deve…

I've been using Gemini-1.5-Pro-2M through Poe for creating e-book recaps and just generally interactively jogging my memory about a prior entry of a book in a series when a new one…

Is the alternative "mass hacking"? I thought all this software did was check a box on some compliance list. And slow down everyone's work laptop by unnecessarily scanning the same …

I'll just leave this here: https://computeexpresslink.org/wp-content/uploads/2023/12/CX... Combined with the fact that Intel created both CXL and Optane, it stands to reason that t…

Xilinx made triSYCL ( https://github.com/triSYCL/triSYCL ), so maybe there's some chance AMD invests first-class support for SYCL (an open standard from Khronos). That'd be nice. B…

> Qualcomm and other ARM manufacturers creaming them on AI stuff That's mostly on Microsoft's DirectML though. I'm not sure whether AMD's implementation is based on ROCm (doubt it)…

These are consumer-grade mobile and laptop chips. That are going into products that won't get sold in the US anyway. Oh, and other Chinese companies, that do sale their products in…

I'm gonna go with Occam's razor. There's no real goal here other than political pandering.

> It would require a reverse lookup structure from address to buffer handle, e.g. red-black tree. Maintaining it would no longer be O(1). Not necessarily. If you are able to map a …

Just curious, how does this work out in terms of TCO (even assuming the price of a Groq LPU is 0$)? What you say makes sense, but I'm wondering how you strike a balance between mas…

That's what I have (RX 7900XT on Arch), and ROCm with pytorch has been reasonably stable so far. Certainly more than good enough for my experimentation. Pytorch itself has official…

The reason is physics. NAND just isn't fast enough (and requires firmware wear-leveling, which can mess up latency) for this to be practical.

it's possible to get <1us with Optane PMem (the dimms) in fio, you just need to use the memory-specific engines so that it avoids the fs/block layer.

The point is that on PMem that is simply "sfence", and not a potentially super-expensive "fsync" syscall... Fsync is an fsync, not a memory barrier...

Yup, works just fine. Overall pytorch on ROCm 5.6 has been working very well. I'm impressed with how stable it is, given how much hate AMD driver stack has been getting.

On my machine with AMD RX 7900XT, it takes ~0.17s per image. Are you using SD Turbo Scheduler node?

On a tangentially related note, big companies often say that they perform pay benchmarking by contributing compensation data to third-parties to then determine the market rate for …

So? The fact that the most successful Arm server product is a proprietary one designed and used exclusively by one company literally proves OP point. It's much easier to support su…