Viewing profile — oelang

VHDL mostly lost the ASIC consumer market and for some that's the only market that matters, but the hardware design ecosystem is much bigger than that. I wonder what AI will do to …

(System)Verilog has delta cycles too you know, they call it an event queue, but it's basically the same. It's the direct variable updates that happen outside of this mechanism that…

It's important to have deterministic simulations and semantics that you can reliably reason about. Both VHDL and SystemVerilog offer this to some extent, but in the case of (System…

VHDL still dominates in medical, military, avionics, space etc. and it's generally considered the safer RTL language, any industry that requires functional safety seems to prefer i…

And I wish you read the article, you're comments are completely off topic.

Jim was involved in the early versions of Zen & M1, I believe he knows. Apples M series looks very impressive because typically, at launch, they are node ahead of the competition, …

Microsoft recently announced that they run chatgpt 3.5 & 4 on mi300 on Azure and the price/performance is better. https://www.amd.com/en/newsroom/press-releases/2024-5-21-amd...

AMD is already competitive on inference

Any sensor that captures a ton of data that needs realtime processing to 'compress' the data before the data can be forwarded to data accumulator. Think MRI or CT scanners but indu…

The transformer engine is a fairly recent development (april this year I think) so I don't think they're very far behind.

They have improved their software significantly in the last year, but there is a movement that's broader than AMD that wants to get rid of CUDA. The entire industry is motivated to…

If you're looking for fair comparisons don't ask nVidias marketing department, those guys are worse than Intel. What AMD did was a true comparison, while nvidia is applying their t…

> refers to scalability of the syntax And the flexibility of the type system and the advanced type inference.

Well you're wrong, you can't run VS Code on the cloud.

There are many examples: a pci-express bus or an application optimized ddr controller or a full tcp/ip stack or a caching/prefetch system or any advanced processor with feedback ..…

> Where did you get %20 percent number? I get the 20% number from a real world case, guys who converted a huge existing vhdl design into HLS with the help of several Xilinx FAEs, t…

This is a very old (I think > 15 years ago) competition, the results say nothing about the situation today, both language have changed a lot. It was a PR stunt by the Synopsys guys…

Let me guess, you were downcasting everything to std_logic_vector? If you have to cast things all the time in VHDL you're not using it correctly. But please enjoy (System)Verilog w…

The verbosity of VHDL isn't 2x it's more like 20% bigger on average and since VHDL 2008 it's pretty much the same. VHDL can be wordy but it also reads a lot easier & it looks more …

No they haven't and they are not even close. OpenCL is a bad language for synthesis. The strength of an FPGA is deeply-pipeline-able sequential algorithms. C-based languages just a…

VHDL is an old version of ADA combined with a build-in discrete event simulator. The syntax, type system, general semantics are all copied from ADA. This is actually a good thing, …

Be honest though, HLS works well for DSP-like applications, not for anything else. Not every digital design is image processing and if it works well you're still sacrificing ~20% o…

I'm surprised that you found it to be inconsistent. Care to give some examples?

How could that dirt be worse than what we have/had on Trump? Does it even matter?

We're 2017, VHDL 2008 was released 9 years ago, and this book is using VHDL 93.