Viewing profile — odmkSeijin

Not with the same exact source files / same software version. But sometimes small changes in the design, or changing tool versions can cause the design to not meet timing. It's jus…

I understand there is some validity with this criticism. Xilinx has always been slow to adopt standard software development practices. But really, Xilinx tools have never cost 'mul…

You have your principles backwards. Non-technical founders should not stay the owners of a technology company if shit happens. The ownership should be usurped by technically profic…

DoreenMichele, I completely agree with your science processes. Someone recently tried to tell me that humans are a two-armed species. I laughed in their face. I said, haven't you e…

James Damore did not write a 'sexist article'. Anyone can read what he wrote and also listen to him explain his thoughts. He doesn't write or say anything that is intentionally ant…

What you are describing is just one aspect of programming with HDL that sounds similar to what one would do with a schematic editor. Fortunately, with HDL you can work at either a …

Uh, yes, that is all true (except maybe the processor with feedback bit is debatable..). I agree with all this, and yet my arguments for why C++ HLS is a good thing remain the same…

Forget about Xilinx marketing. I am curious, what did you find causes a design fall outside the '20%' usecase situation? Are you talking about asynchronous clocks? feedback? IO con…

I don't agree with this, but I think I see what you are trying to say. I think typically a full design would include some interface portion with maybe DMA or PCIe or whatever that …

Both. The differences are not that great. I don't believe anyone who says they can done something in one that can't be done in another, they just don't now how to do it. After star…

I programmed FPGAs using both VHDL and Verilog for many years. Recently I have started at a start-up where we predominantly program using C++ HLS. I never want to go back to full-t…