Viewing profile — nickmqb

Shameless plug: I had a similar impression when looking at nMigen, but wasn't super happy with Verilog either, so I wrote a new HDL called Wyre [0]. No metaprogramming, but a Veril…

It did cross my mind. However, a problem with that approach is that evaluating such a formula is too costly/inaccurate on a small FPGA like this, which just has 8 DSPs (that can on…

Most textures look fine despite the 4-bit quantization, but color artifacts/hue change do become more apparent when multiplying with a light factor (to darken the textures on the b…

VGA is an analog protocol, but the FPGA can only output a 0 (GND) or 1 (3.3v) on its I/O pins. I'm using a Digilent VGA Pmod [1] which uses a set of resistor ladders to map each co…

That's a good observation! This technique is also known as "racing the beam". The problem is a mismatch of refresh rates; the VGA display operates at 60 Hz but the ray tracer is no…

Yes, I am. This also means that any open source distribution won't include those textures. However, if I do end up open sourcing the work I'll make sure to include instructions for…

Yes and no. The design includes a custom built 16-bit CPU, which uses a custom instruction set, which I wrote an assembler for. There is a small 4kb bank of RAM that contains a pro…

That's a good idea. The two analog sticks on the GC controller would be an improvement over the single stick on the N64 controller for movement in 3D. I think that the main benefit…

Just do it ;). I don't have a blog post on how I got started, but you gave me the idea that perhaps I should write one. In terms of hardware, I'm using an iCEBreaker dev board [1] …

In terms of I/O pins that should actually be fine (current pinout: VGA (14x), SPI (4x), CLK (1x), N64_controller (1x)), though I'm still working on the project and I don't think it…

There are definitely FPGAs that are a lot more capable than the FPGA that I'm using. For example, see my reply to flatiron here: https://news.ycombinator.com/item?id=25172781 While…

I probably won't port it to other platforms, however, as I wrote in another comment, I am considering open sourcing it when it's done, so others can port it if they like. I just lo…

Yes, I'm using Wyre for this. Feedback is always welcome, so once you've had a chance to try it, don't hesitate to let me know what you think!

Thanks! That's correct, I built the ray tracing "GPU" from scratch. It's highly optimized because it needs to trace 256 * 128 * 30 = 0.98 million rays per second on very under powe…

Yup, that's correct, the design is implemented in Wyre, which is a hardware definition language that I created. The language compiles to Verilog so it can work with existing hardwa…

The FPGA that I'm using for this (the Lattice iCE40 UP5K) is really limited when it comes to RAM, which is the main constraint when it comes to world size. As per the title, there'…

The screen is connected to the FPGA over VGA. The output resolution is 1024x768 @ 60Hz, but the 3D portion of the screen is rendered at 256x128 @ 30Hz. The design consists of a cus…

You're not giving the older generations of programmers enough credit here. While it is true that strong typing is a requirement for the best performance (and this remains so), the …

A list of widgets, with each widget having a x, y, width and height.

Do UIs need to be trees? How do things change if we were to use a list instead? What becomes easier/harder? Layout calculations might become slightly more expensive, though it seem…

I have a somewhat controversial opinion on this. This paper, like some others that I've seen, treats parsing as an academic/algorithmic topic. Given some token stream we'd like to …

This FPGA is not open source by design, but this project seems fairly complete: http://www.clifford.at/icestorm/ "Project IceStorm aims at documenting the bitstream format of Latti…

Does anyone know of any minimal TUI libraries? Something in the spirit of a VGA text buffer, that allows the user to manage their own cell buffer as a block of memory, and allows t…