Viewing profile — mithro

Hackerfab.org is a bunch of people trying to create a reproducible version of Sam's work.

https://www.linkedin.com/posts/hirosh-dabui-a5367443_linux-r...

The design was taped out on the first wafer.space run (see https://github.com/wafer-space/ws-run1 ) but I have not heard if it actually worked or not.

wafer.space has just opened our first pooled manufacturing run of GF180MCU with the purchase deadline of 28th Nov 2025. Think of it like OHS Park for silicon! You provide a 20mm2 d…

Things like my https://wafer.space ($7k USD), TinyTapeout.com ( There are a huge number of designs from Tiny Tapeout which are all public - see https://tinytapeout.com/runs/ The de…

There is plenty of updates on the website at https://theopenroadproject.org/ - Including a pretty good report on what happened in 2024. Also take a look at the Open Source EDA BOF …

The team at Antmicro put together this pretty cool visualisation flow for this stuff using only open source tools -> https://antmicro.com/blog/2023/11/open-source-signal-integri...…

https://antmicro.com/blog/2022/01/fomu-keystroke-injector/

I also have a general offer to send people who contribute to the open source FPGA tooling and ecosystem free Fomu boards.

The Tomu family also has; - The Fomu (FPGA Tomu) - https://fomu.im/ and https://workshop.fomu.im/ - The Qomu (ARM+eFPGA Tomu) - https://tomu.im/qomu.html - The Somu (Secure Tomu) -…

I afraid I don't recall the status of DSP blocks in the open source toolchains for Xilinx hardware. Even if the basics are supported I'm sure there are plenty of DSP features that …

I have a Google Doc at https://j.mp/softcpus-on-fpgas > which includes a bunch of information about what type of performance has been achieved on modern Xilinx FPGAs. You can gener…

The open source toolchain doesn't quite support the PCIe interface yet but all the other stuff should work in theory. The best place to see what works is the F4PGA examples documen…

When did you last check? The Yosys+VPR toolchain currently supports a full Linux capable SoC with Ethernet and DDR memory on the Arty A35T (which has a Xilinx Artix 7 part), see th…

While the news seems to focuses on ML and RISC-V, there is a huge amount of *other* activity in the silicon space. With [Google working to improve the open source EDA tools + PDKs …

Checkout Surelog - https://antmicro.com/blog/2020/12/ibex-support-in-verilator-... and the more recent usage in https://github.com/siliconcompiler/siliconcompiler

On a semi-related note, Google has also been investigating in improving support for SystemVerilog support in open source tooling -> https://opensource.googleblog.com/2021/09/open-s…

All these are good points but missed a key thing. The interchange format includes a computer readable description of the FPGA which tells the tooling what is available inside the F…

Except that nextpnr is one of the tools supporting the interchange format and you can see the status at https://symbiflow.github.io/fpga-interchange-tests/

Project F ( https://projectf.io/posts/fpga-graphics/ ) has a lot of cool examples with visually interesting output.

If you are motivated by learning rather than practical usage, FPGAs are a great way to learn more about how things like CPUs or peripherals can be designed. It is also a way to und…

Google has been working on solutions to make it easier to explore this type of issue (and mitigation techniques), see https://opensource.googleblog.com/2021/11/Open%20source%20DD..…

Google is working on platforms to make this easier to explore this problem, see https://opensource.googleblog.com/2021/11/Open%20source%20DD...

Does Speedify have an open source client? I'd be interested in paying for the service but not willing to run closed source software locally and then send all my traffic to it.