Viewing profile — learyg

I am not personally a manager / hiring manager, but this is the job posting for SW/HW codesign positions in the south bay area CA -- speaking as an IC, it has been a very enjoyable…

One of the things we have on our short list is "good FFI" for instantiating existing RTL blocks (and making their timing characteristics known to the compiler) and making import fl…

Hi, one of the collaborators here! One question to consider, and one that I consider pretty frequently, is what the hard difference really is between HLS and RTL. It seems up to in…

Thanks again for the detailed thought! We actually [developed more advanced bit slicing syntax]( https://github.com/google/xls/blob/1b6859dc384fe8fa39fb901af... ) since that exampl…

Hi, one of the collaborators here, thanks for the good points. We have been targeting some Lattice FPGAs for prototyping purposes, but we've mostly been doing designs for ASIC proc…

Did you see the "using tfcompile" section of the docs? https://www.tensorflow.org/versions/master/experimental/xla/... If you're looking for more detailed information that's missin…

It's gpucc, so it builds from LLVM when you enable XLA in the TF configure step. Trying to understand: you don't want to ship a compiler library on principle, or is it some kind of…

AOT for GPUs is doable. Do you have a killer use case? For CPU, mobile code footprint reduction was the driving force.

The XLA and vanilla TF variants appear to be the same here: https://github.com/tensorflow/tensorflow/blob/2c8d0dca978a24... https://github.com/tensorflow/tensorflow/blob/2c8d0dca97…