Viewing profile — jeff_ciesielski

We do a fair bit of FPGA design in SpinalHDL, and have taped out several ASICs with parts of the design done in SpinalHDL at my dayjob. In general: No, alternative HDLs don't see a…

Like any time you get off the beaten path, there are rough patches, but to paraphrase another comment in this thread "Nim is just C", so anything that felt a little awkward just me…

> In what way? Comptime should be generally capable of anything macros are. I started to reply to this with 'Comptime is generally capable of doing anything that Nim's templates ca…

I used Zig (not MicroZig, just rolled my own HAL) for the bootloader and firmware on a soft RISC-V SOC + custom peripherals recently and had somewhat mixed, though positive feeling…

This is a nice breakdown, however it is leaving out one interesting piece: Active slew rate controllers. In some cases where you need to exceed the typically allowed bus capacitanc…

I hate to give an 'it depends', but it depends. Typically, no. In SPI all lines are actively driven high or low rather than an open drain configuration. The bus master drives SCK (…

(From someone who is working on a rv32im implementation in Clash) I really love writing RTL in haskell when compared to verilog/vhdl, but as a language I think it suffers from the …

I wrote something similar a while back (also in nim): https://github.com/Jeff-Ciesielski/synesthesia When I stop being so darn busy, I do want to revisit my original project of doi…

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