Viewing profile — jared_hulbert

Just ran a version with 6 prefetching threads. I get 5.81GB/s. Same as the io_uring with 2 drives, but still a lot slower than the in memory solution.

Someone else suggested this, results are even worse by 2.5s.

When I run the 50GB in-mem setup I still have 40GB+ of free memory, I drop the page cache before I run "sudo sh -c 'echo 3 > /proc/sys/vm/drop_caches'" there wouldn't really be any…

The io_uring solution avoids this whole effort of mapping. It doesn't have to map the already-in-RAM pages at all. It reuses a small set of buffers. So there is a lot of random cac…

I get that. But I do actually show a scenario where accessing data from memory using a very standard mechanism IS slower than a newer but equally standard way of accessing data fro…

Adding MAP_HUGE_1GB and not MAP_HUGETLB does compile and run for me. Not convinced that its' actually doing anything. Performance is the same.

Not by a ton but if you add up the DDR5 channel bandwidth and the PCIe lanes most systems the PCIe bandwidth is higher. Yes. HBM and L3 cache will be higher than the PCIe.

Hmm. tmpfs was slower. hugetlbfs wasn't working for me.

spdk and I go way back. I'm confident it'd be about the same, possibly ~200-300MB/s more, I was pretty close to the rated throughput of the drives. Io_uring has really closed the g…

YES! gcc and clang don't like to optimize this. But they do if you hardcode the size_bytes to an aligned value. It kind of makes sense, what if a user passes size_bytes as 3? With …

I worked on SSDs for years. Too many people are suffering from insufficiently solid values of "disk" IMHO.

int fd = open(filename, O_RDONLY); void* buffer = mmap(NULL, size_bytes, PROT_READ, (MAP_HUGETLB | MAP_HUGE_1GB), fd, 0); This doesn't work with a file on my ext4 volume. What am I…

The original blog post title is intentionally clickbaity. You know, to bait people into clicking. Also I do want to challenge people to really think here. Seeing if the cached file…

https://www.intel.com/content/www/us/en/io/data-direct-i-o-t... AMD has something similar. The PCIe bus and memory bus both originate from the processor or IO die of the "CPU" when…

I tried with the log scale before. They failed to express the exponential hockey stick growth unless you really spend the time with the charts and know what log scale is. I'll work…

Would this actually create huge page page cache entries?

Lol. Thanks.

Oh man... I'd have look into that. Off the top of my head I don't know how you'd make that happen. Way back when I'd have said no. Now with all the folio updates to the Linux kerne…

Cool. Original author here. AMA.

In this context CXL is kinda storage and kinda higher latency RAM. It's latency is worse than standard DDR5 DIMMs but the bandwidth is on the same trajectory as storage/networking.…

We are seeing more SRAM in the form of CPU caches, this is one of the things that is actually scaling still. Are you asking why not use SRAM in something like a DIMM? You could do …

Original author AMA

https://www.bitflux.ai/blog/memory-is-slow-part2/

I found https://aokumo.ai/ Who else?

I'm launching this project, looking for feedback. Seems obvious to me that Agents are, should be, or will soon be a part of every SRE/DevOps workflow like I do in this demo. Who is…