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j_seigh

HN member
Joined
Fri, May 16, 2025, 5:22 PM UTC
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34
Public activity
35 items

About j_seigh

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Recent public activity

  1. comment
    Comment #48872007

    Sort of. Basically you have a situation where one thread needs to see another thread's memory accesses in sequential consistent order. If you can determine the other thread has syn…

  2. comment
    Comment #48833000

    For hazard pointers it was proposed here https://groups.google.com/g/comp.programming.threads/c/XU6Bt... I did a POC afterwards. For linux it was a bit PITA since /proc text had to…

  3. comment
    Comment #48093291

    Lighting rods also work by dissipating the local electric potential and reducing the likelihood of a lightning strike. That's why they are pointed, or fractal in the newer ones. Fr…

  4. comment
    Comment #47705454

    Couldn't traceroute run the entire TTL range in parallel, assuming the destination host was reachable and replies are disambiguable? I always hated waiting for traceroutes with lot…

  5. comment
    Comment #47562350

    My impression was LL/SC had forward progress issues due to the difficulties of preventing false sharing of the locked memory reservation region. Updates into that region would keep…

  6. comment
    Comment #47341001

    It seems almost nobody can spell lose correctly anymore. I assume it's deliberate.

  7. comment
    Comment #46420637

    The comments about HFT needing tightly synchronized clocks got me thinking. Back in the day, way back in the 80's, IBM replaced the VM with VMXA. VM could trap and emulate all the …

  8. comment
    Comment #46404901

    Ok,so people use NTP to "synchronize" their clocks and then write applications that assume the clocks are in exact sync and can use timestamps for synchronization, even though NTP …

  9. comment
    Comment #46293074

    I did a lock-free MPMC ring buffer with 1 128 bit CAS and 1 64 bit CAS for enqueue and 1 64 bit CAS for dequeue. The payload is an unrestricted uintptr_t (64 bit) value so no way t…

  10. comment
    Comment #45972810

    Paywalled, but if you are familiar with the ABA problem in lock-free programming you can pretty much figure things out.

  11. story
  12. comment
    Comment #45781767

    Coherent cache is transparent to the memory model. So if someone trying to explain memory model and ordering mentioned cache as affecting the memory model, it was pretty much a sig…

  13. comment
    Comment #45641926

    How is this different than something like https://www.espertech.com/

  14. comment
    Comment #45424424

    I'm assuming they're using an unbounded MPMC queue. With GC you can use a lock-free queue, otherwise you have to use mutexes, or reference counting which is nearly as bad.

  15. comment
    Comment #45414177

    I did do an actual lock-free MPMC ring buffer implementation as an exercise. I used that to make blocking bounded queues using various synchronization mechanisms, mutex/condvars an…

  16. comment
    Comment #45332779

    Only using way more bits. The original IBM lock-free stack algorithm assumed 32 bits was safe because it would take 100 years for a 32 bit counter to wrap at the time. Now it's les…

  17. comment
    Comment #45151567

    I did find some links to some of my old posts on restartable sequences for user space rcu. Looked into using unix signal handling but it was pretty problematic to put it mildly. De…

  18. comment
    Comment #45044086

    It's worse than you think. I've closed PayPal accounts and opened new ones with a different email address and PayPal updates the merchants who've been spamming me with the new emai…

  19. comment
    Comment #44988360

    I don't think it has to be. Conceptually it's just a couple of queues. There's a software equivalent of the Peter Principle where software or an API becomes increasingly complex to…

  20. comment
    Comment #44966840

    https://groups.google.com/g/comp.programming.threads/c/XU6Bt... https://groups.google.com/g/linux.kernel/c/gk6AUkXR9As/m/-1W... Yes, I am aware of the asymmetric memory barriers tr…

  21. comment
    Comment #44960881

    Bakery locks are good for spin locks. They're more cache friendly. Plus you can do reader/writer spin locks. They're going to be strictly FIFO though. I guess you could tack on a f…

  22. comment
    Comment #44594236

    Here's an interesting scheme. Some credit/debit card merchant accounts can arrange to get updated card info if your card expires and/or gets replaced. So if the merchant is a bad a…

  23. comment
    Comment #44551470

    One of the few places I get a citation. It's where the idea of asymmetric memory barriers came from. RCU is used as the quiescent states are context switches which gives you a memo…

  24. comment
    Comment #44366012

    ChromeOS flex. It will run on hardware that even Linux complains about. I've even installed it on a Chromebook that stopped getting updates. Though, you have to replace the firmwar…

  25. comment
    Comment #44242508

    Thread local vars would be used with lazy initialization. Clean up might be a little tricky depending on what implementation of thread local you use. Thread local support is not as…