Viewing profile — j_coder

Who uses Plaid for ACH verification must start to think on alternatives. Visa blocked PayPal to growth its ACH payments a few years ago.

I can imagine on a few decades company's data center on a single square meter chip :)

So Google don't test for load? They should ;)

You need to find as soon as possible trusted people that can tell you how bad is your idea/game play/sound/narrative so you can fix it or do something else. Most will just be polit…

Very advanced civilizations could learn how to create targeted worm hole like structures to send information through it using real world physic rules that we don't know yet

It is amazing how each new version of Android has a complete new UX and none of them are actually good. Google is basically a back-end company incapable of doing good UX (if it is …

It is not the OCR that is costly. It is the JavaScript execution to render the page so you can do the OCR. You can even increase the JavaScript execution cost if suspicious. You wi…

Yes. The idea here is to make you dependent on OCR (you also have to find where is the information as the page design changes) and to waste a lot of your server resources making it…

It is "easy" to block scraping. Make it very costly to scrape: - Render your page using canvas and WebAssembly compiled from C, C++, or Rust. Create your own text rendering functio…

What I don't understand is why the kernel patches and microcode updates are still been worked out today. They had 6 months to work on it. No secret channel to communicate with Linu…

It would make sense if it was the only alternative as the kernel can handle it. The appropriate behavior is to remove all traces of the speculative execution including cache hits.

I would never send to him :)

So it is a game over here. Unless Intel can change the microcode to force a page fault in this case.

I thought that: mov rax, [Somekerneladdress] would trigger an interrupt even on speculative execution as described on https://cyber.wtf/2017/07/28/negative-result-reading-kernel-..…

I suspect a better solution instead of KPTI is to evict all user space pages from cache when an invalid page access happens if fault was caused by read/write kernel space pages. My…

Not having a central controller multiple subsystem vendors would have to cooperate using an agreed DMA communication protocol to monitor you and send the information back using the…

You are right. The best approach is to evict all user space pages from cache when an invalid page access happens if the page fault was caused by the software trying to read/write k…

So in all cases just evict the entire process memory from the cache when the interrupt is raised when reading from a protected memory. The performance penalty would apply only to m…

For software that requires self-modifying code to run the existing Linux kernel patch would apply (performance penalty). If there is other ways to flush the cache it is necessary t…

I know it was scheduled but the information on the links are public and prior to the scheduled disclosure. A hacker could figure out the problem by reading the available informatio…

Isn't possible for the kernel to patch all clflush instructions when the software is loaded to keep a circular list of all evicted addresses that would be evicted again on the inte…

Looks like the information was somewhat public available since middle of the last year on https://cyber.wtf/2017/07/28/negative-result-reading-kernel-... and http://www.cs.binghamt…

It is the opposite. Batteries degradation acts as an internal resistance at rest (Rd) that increases over time. There is a second resistance (Rc) that increases as you discharge th…

First? https://www.vice.com/en_id/article/3knb7n/kidnappers-around-...

It is about battery life. This is how the battery should be measured: 100% -> Doesn't charge more 0% -> Do no provide enough voltage/current for safe operation at current power mod…