Viewing profile — gsmecher

If AI does anything to the EDA space, I hope it helps break the chokehold the "big 3" have on tooling. Any startup that threatens their dominance gets acquired and disappeared. I a…

I love that VHDL formalizes Verilog's pragmatic blundering, but emphasizing delta-cycle ordering is "inside baseball" and IMO bad marketing. VHDL's approach is conceptually clean, …

Towards the end of my EE degree in the mid-2000s, I hoodwinked Ralph into dropping by my dingy east-Vancouver rental for a tech demo. I was trying to find a home for my thesis rese…

There's nothing wrong with an open clone when everybody is acting in good faith. (In fact, "good faith" does not even necessarily mean "according to the letter of the law in $juris…

Oh my - good find, and also, eek. Analogy: https://datasheet.lcsc.com/lcsc/2302211830_analogysemi-ADX11... TI: https://www.ti.com/lit/ds/symlink/ads1115.pdf Analogy's datasheet is …

These experiments are always unique, and each is interesting in its own way. Can you comment on the use of asynchronous code rather than generators? For example, here's a throw-awa…

I've pushed a couple of boulders up this particular hill, and none of them have stayed there. Trouble is, Python is a great stack for communicating with networked instrumentation -…

You should talk with Metrics (metrics.ca), who are walking a similar path and have a few years' head start. They are a solid team and are likely to be open and friendly about their…

The "language wars" narrative feels pretty played-out, so I'm not going to get drawn into it. In the software world everyone seems to recognize that different languages have differ…

From 2020. This article is hagiography - while it's worth celebrating how far HDL has come, it's also worth looking into what's holding us back. Verilog is one of those things, so …

Xilinx/AMD doesn't make overt donations any more AFAIK, but they still subsidize hardware as a loss leader and for academics. For example, academic groups can buy the RFSoC 4x2 boa…

I posted the Reddit link because it wasn't my insight - but I agree it's a dubious source. That doesn't make it wrong. (I'm not certain it's right, either - it's an interesting cla…

> This is dead right, the enabling technologies like You fundamentally misunderstand. Soft core CPUs aren't enabling technologies and haven't been for decades. They are plumbing, l…

According to a Reddit comment [1], this is the same MicroBlaze RTL with a RISC-V instruction decoder in front of it. This seems crazy from a let's-make-the-best-RISCV-core perspect…

> Depends on what AMD does with Xilinx. Currently the AMD/Xilinx dynamic seems to reverse this: "Depends on what Xilinx does with AMD". AMD's software roadmap for AI/datacentre lea…

The integrated Ethernet switch is only as useful as its software stack - I say this after an excruciating decade with TI's Sitara devices (and the built-in CPSW ethernet switch.)

On FPGAs, a register file probably fits better into distributed RAM than block RAM. On Xilinx, for example: a 64-bit register file doesn't map efficiently to Xilinx's RAMB36 primit…

> What's your issue with Shockley btw? Nobody can pick fights with Shockley any more (he's dead) - but Shockley is almost a household name, and Bardeen/Brattain's aren't. It's wort…

> everything comes down to datapath. Ain't that the truth. However: Xilinx's DSP58 blocks (Versal devices), and older Intel DSPs, do integrate floating point into the DSP tiles - w…

Also discussed here: https://old.reddit.com/r/FPGA/comments/15fnb6u/egpu_a_750_mh...

Project X-Ray [1] and Project U-Ray [2] are the best source for configuration details that Xilinx/AMD doesn't publish. These projects focus, respectively, on the 7-series and Ultra…

Interesting. If you ever do track down the scuttlebutt on poor-performance internal regulators, please pass it along? I'm not terribly hard to find.

On the mystery voltage regulator: most OCXOs also provide a regulated reference output on the pin that's marked N/C on this device. This reference is important because the tuning v…

The software/firmware/hardware stack is layered. Here's what has worked for me, for several FPGA-based instrumentation applications. * Integration level: this is typically Yocto or…