Viewing profile — ekiwi

One solution is e-bikes which are getting better every year and will allow you to go quite far without breaking a sweat.

The 32-bit aligned instruction assumption is probably baked into their low-level caches, branch predictors etc. That might mean much more significant work for switching to 16-bit i…

They verified the protocol, not the actual implementation: https://github.com/rosenpass/rosenpass#security-analysis This is still a pretty neat result! End-to-end proofs from high …

My biggest question after looking at the readme: What happens if your computer crashes while dura is making a commit? Can it corrupt your local git repository? From my own experien…

> nuclear waste is not waste There is a lot more to nuclear waste than just the fuel rods. Lots of materials that are either used by workers at the plant or part of the plant becom…

> if the two of them don't decide to add their own proprietary "extensions" to the language. icc has always had its own dialect of C++, which in practice means that there is "C++" …

> At best you can do the same with one reduced canonical simplified verilog source-to-source translation. Parsing Verilog and generating valid Verilog is fairly difficult. If you w…

> Access to any global variable should always occur direct from memory. What if your function takes a pointer that might be pointing to a global variable? Does that mean that all a…

> Chisel is therefore it's "synthesizable subset". Chisel is not synthesizing Scala. It is just a library implemented in Scala that allows you to create a data structure that descr…

Chisel imho solves the "synthesizable subset" problem quite elegantly: All Chisel constructs are simple, synthesizable circuit elements and boolean functions (+ functions on fixed …

Chisel is not HLS. It is a Scala library that lets you generate circuits on an RTL abstraction level. That means that you explicitly define every state element like registers and m…

Did you see the work being done on CIRCT? https://github.com/llvm/circt I remember one of the reasons you did not want to use firrtl was that its compiler is implemented in Scala a…

It was in fact the EdgeTPU (which is different from the TPU used in data centers). The talk from a google engineer can be found on youtube: https://www.youtube.com/watch?v=x85342Cn…

I think the hardest problem is contributing changes back upstream. With hardware, people are a lot more paranoid about introducing new bugs and I feel like that sometimes makes col…

Sounds like nmigen might be a good open source successor to the project that you describe: https://github.com/nmigen/nmigen There are lots of open-source (n)migen components availa…

If you hit the Windows key on Gnome 3, you can type the name of a program, file or system setting and it will generally find it.

Glacial was one of the entries for the 2018 RISC-V SoftCPU Contest, but I think it wasn't ready by the deadline. If you look at the winners there was another 8-bit CPU with a RISC-…

How do you deal with structured formats, like XML? In JQF you would just write a XML generator (see their examples). If you just use the "sequence of bytes" approach as AFL does, t…

If you are interested in fuzzing your Java code, you should also have a look at the JQF project which directly integrates with junit tests: https://github.com/rohanpadhye/JQF

This is the latest paper on BOOM: http://people.eecs.berkeley.edu/~krste/papers/SonicBOOM-CARR... It has some comparisons so you can judge for yourself. Of course, since this is a …

> It used to be you could email a patch to someone and that patch would get reviewed and committed. Yes, but 1990 is also when this study came out: https://ftp.cs.wisc.edu/par-dist…

You might be interested in this work which integrates a programmable fabric directly with a MIPS core in order to speed up inner loops: http://brass.cs.berkeley.edu/garp.html

You also have to keep in mind that modern flows can already automatically place more area/power efficient but slower transistors on the non-critical paths. Thus signals can get bal…

The problem with delay slots is that their optimal size is somewhat tied to the particular micro-architecture. I.e., different MIPS CPU implementations would have different optimal…

> I thought Berkeley's BOOM is way more advanced implementation of RISCV than VexRiscV and it is written in Chisel3. It is a lot more advanced and thus harder to get started with t…