Viewing profile — e7h4nz
e7h4nz
HN member- Joined
- Sun, Oct 26, 2025, 10:19 PM UTC
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About e7h4nz
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Recent public activity
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Ts-rest – what happens when a 3.3k star OSS project goes dormant
Last June, I switched my company's API stack to ts-rest — the contract-driven type-safe REST library for TypeScript. Today I'm staring at a repo that hasn't shipped a release in 11…
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Comment #47833744
We had a similar journey with Neon's branching. Initially it was a huge win for our CI workflows — spinning up an isolated, production-shaped database per PR made migration testing…
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Comment #47775980
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Comment #47775917
If AI agents can proficiently use whatsapp I would assume that two-thirds of the people chatting with me in my contacts are actually just bots messaging me.
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Comment #47582276
In this problem domain, I believe humanity is still in a very early stage. What we can do is treat the agent and its operating environment as a "black box" and audit all incoming a…
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Comment #47576284
Did you actually read this article or try to understand what OneCLI does?
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Comment #47575485
Removed microservices and RPC, keep all TypeScript codes in a single monorepo. Avoiding `any` and using ts-rest automatically keep types synchronized between the web and frontend a…
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Comment #47575085
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Comment #47574789
I worked on a core Spring Boot project for five or six years at a very large enterprise. In my opinion, the most dangerous thing about this framework is that it makes its core user…
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Comment #47572113
Agreed. we hit some wired case on Adreno 530, ran into bizarre GPU instruction set issues with the compute shader compressor, that only manifested on Adreno 53x. Ended up having to…
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Comment #47571837
I really resonated with the end of README.md. I have a huge stack of embedded development boards at home—all kinds of SBCs, microcontrollers, FPGAs, and more. Over the years, as a …
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Comment #47571026
On a practical level, you're right, most of my team's work is done in Verilog. That being said, I still have a preference for the VHDL simulation model. A design that builds correc…
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Comment #47570930
The irony of hardware image compression is that the devices that need it most are typically older, bandwidth-constrained SoCs. However, these are precisely the devices that do not …
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Comment #47570858
The Delta Cycle logic is actually quite similar to functional reactive programming. It separates how a value changes from when a process responds to that change. VHDL had this figu…
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Comment #47569366
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Comment #47569116
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Comment #46687332
hi, I'm VM0's developer. Happy to answer your questions. I fully agree, without clear architecture docs, I wouldn't trust an infra service either. We're working on technical docume…