Viewing profile — dspwizard

I wish I could upvote this twice !

It is really puzzling how a GPU could work in such latency constrained environment like RU. On the cost side - RU are built with on chip SRAM as a processing memory for cost,latenc…

VLIW works great when you have predictable & short latencies of memory accesses - you will not find DSP designs that do not use TCM (core local SRAM). So you program DMAs input dat…

TI C2000 is one example

Cadence DSPs have C++17 compatible compiler and will be c++20 soon, new CEVA cores also (both are are clang based). TI C7x is still C++14 (C6000 is ancient core, yet still got c++1…

Most of VRAN sites will be still DRAN (distributed RAN -server on site). CRAN (centralized RAN) is a fairy tale so far and works very few scenarios like very dense urban. Still we …

The most amusing part is that Huawei developed 5G tech on its own - nokia has shit and e/// is not better. Even in regards of 4G massive MIMO tech - Huawei is years ahead of other,…

Huawei is far ahead of others in mMIMO technology and have this implemented in their BTS boards, although right now it is done in FPGA not ASIC.

I had to register to comment about TI "quality" and friendliness ;-). Their SoCs are ridden with HW bugs and TI will not put every HW bug to errata - e.g. their infrastructure pktd…