Viewing profile — dougall

Hi, author here. My version definitely shouldn't be faster unless something very weird is going on with the runtime (though I think with the benefit of hindsight some further optim…

It's fun :)

Yeah, exactly this. To try to make it more "concrete", compilers tend to end up processing an absurd mess of code, that does things that superficially look silly, due to extensive …

Author here - I believe this 2020 post resurfaced as known-bits optimisation was recently added to PyPy (Python implementation using a JIT compiler), which this thread discusses: h…

Awesome! I'm always happy to hear people are interested in SVE :) (And yeah, creating technical documentation that a large company should have created themselves has somehow become…

Heh, I'd have called it the Arm SIMD Instruction List, but Arm have been aggressively enforcing the Arm trademark [1], so I settled for A64 (the official name for the instruction s…

I hope it's useful, though I think most people care about the "Advanced SIMD" (Neon) instructions, which I'd also like to do. I started with SVE because I wasn't already familiar w…

It is a trade off, but a lot of processors have free offsets from loads, so pointer chasing is almost always free. On ARM, "ldr x0, [x1]" just becomes "ldur x0, [x1, #-1]" - same s…

The tag bit can be inverted. V8 uses 1 for pointers, 0 for integers - you're usually loading from constant offsets from pointers anyway, so that mostly folds away nicely. Then: x +…

Yeah... I don't know if you saw Rodrigo Branco's damning "The Microarchitectures That I Saw And The Ones That I Hope To One Day See": https://www.youtube.com/watch?v=WlcQrx7VK00 ht…

Browsers use multiple processes for security and reliability, not as an alternative to multi-threading. They extensively use multi-threading for performance (as does a lot of other…

Yeah – ARM specifically added EOR3 and BCAX instructions to accelerate SHA-3 hashes, both of which can be handled by VPTERNLOGD.

Is there a reason you call out Discord and not GitHub?

Good point, it's likely that a high-power in-order chip could go faster. Do you know of any examples of high-power in-order cores I could compare to?

Alas, security generally isn't so important. How many times have you been hacked by a side-channel exploit? (Or people you know? Or any publicly documented case?) Are you going to …

Nice! Sorry if this comment is overly pedantic, I just enjoy having an excuse to talk about assembly. It's worth noting that 0x80000000 would pass this "is zero" check. (I think th…

Though it'd be preferable to do: cmp wzr, w19 // set the carry flag if w19 is zero adc w8, w19, w19 // w8 = w19 + w19 + carry

Some: https://news.ycombinator.com/item?id=35301630

Really? Is there case law to this effect? These things happen, and have value, but I wouldn't have considered them as "given as a quid pro quo" or "mutual promises".

It's a huge issue, but multi-threading only helps with latency, not energy.

Then do that. It's not a video codec. The problem is computation power is increasing much more slowly than bandwidth, and is likely to continue to. 8K PNGs (by my napkin calculatio…

Thanks! It's a tiny contribution compared to Alyssa and Lina's development and reverse engineering work, but it's been very educational and rewarding work so far :)