Viewing profile — diamondlovesyou

Not if you can't prove anti-aliasing properties, which wasm doesn't carry.

> Now why can't compilers do this sort of thing automatically? They do - they just can't assume GFNI instructions are present unless you explicitly say so: https://godbolt.org/z/eY…

That won't be located on the stack either. The underlying buffer will be a TU local - ie static and not rx

> This post makes it seem like the pass ordering problem is bigger than it really is and then overestimates the extent to which egraphs solve it. It isn't so much for SoTA implemen…

I don't use credit cards for the credit; in fact mine are completely paid for every statement. They are used for the customer protections and other provided "free" benefits. If som…

Less area means less sources of interference for others (this property is also true in the other direction). So the attenuation reduces the signal area, and stronger attenuation le…

> Why is cooperation unlikely? AFAIK it’s not too hard to make a compiler support a function attribute that says “do not optimize this function at all” Compilers like Clang actuall…

GB6 will use the Zen4's AVX512, which Zen2 doesn't support.

Fast is relative here. These are microcoded instructions, which are generally terrible for latency: microcoded instructions don't get branch prediction benefits, nor OoO benefits (…

AMD's string store is not like Intel's. Generally, you don't want to use it until you are past the CPU's L2 size (L3 is a victim cache), making ~2k WAY too small. Once past that po…

I have been very happy with my Minisforum Venus UM790, though I use it as a mobile computer since I can just throw it into my backpack. It's been great to have access to AVX512 on …

> It is not a language flaw. C++ requires types to be complete when defining them because it needs to have access to their internal structure and layout to be in a position to appl…

The power of the optimizations available to C++ are what make it so fast (see how slow debug mode is vs -O2/etc), and what allow C++ to be fast in the face of common/easy-to-unders…

https://archive.li/ZN5MJ

CISC vs RISC doesn't matter. An ISA should ideally be a healthy mixture of both (citation needed). Arm64 allows memory operands, "just" like x86; but it still has code size issues.…

Sadly, nobody can run from memory management.

> Like almost any thorny military problem of the 1950s, the solution was the application of nuclear bombs. Magnificent.

I don't think scalable vectors is particularly useful feature, especially compared to what compilers have to go though to support it. It's much more useful to be able to do "more p…

Add a period to the end of the sentence and aberration is gone. "맙소사, 절대평화주의자들도 가끔 존재 자체가 고통이라 해도 남에게 해를 끼치는 행동을 하는 것 같아요."

See AMD "Smart Memory" a.k.a. PCIe Large Bar. This expands the amount of GPU memory that the CPU can directly access, usually to the GPU's entire memory range (ordinarily only ~256…

> By the time of the second gulf war, the F-14D cost 20% more per unit than the F-18E, and some 80-100% more to maintain. I'm not sure how you're concluding that the taxpayers were…

Naw, just use {pointer, length} tuples. Crisis averted.

GB4/5 are... not a particularly high quality codebases. I can't offer anything more than that, but, well, lets just say that GB4/5 is my least favorite benchmark as a compiler engi…

HBM GPUs are better off because the memory cores are in the same package as the compute cores. So they get the same amount of cooling love as the compute cores enjoy. At least in t…

> But if you get it a little too close together, it goes boom. It won't go boom. One of the difficulties (of many) of the Manhattan project was that it was really really difficult …