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clausecker

HN member
Joined
Wed, Sep 13, 2023, 5:24 PM UTC
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335
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113 items

About clausecker

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Recent public activity

  1. comment
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    Comment #48082468

    Go had panic/recover right from the get go. Nobody “caved.” And indeed, you are free to use panic/recover for error handling in your code. That was always allowed. That said, the k…

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    Comment #48082420

    Really bad idea. Silently returning some (the wrong) value is always worse than catching the error right then and their and panicking. A panic is a noticeable symptom of something …

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    Comment #48082381

    > No it really doesn't. It litters your code with if statements that are all just about the same, except that one that needs to be different, and you go blind looking at them all a…

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    Comment #46428553

    You can find the first set bit in an integer with a machine instruction, it's completely branch free. gcc has __builtin_ctz() for this. You'll either need to iterate over all set b…

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    Comment #46413236

    So I've thought about it and I don't really feel like spending more time to convince you that this works. If you have questions I am happy to answer them, but please write your own…

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    Comment #46413228

    This does track the state. If you want to track it across multple vectors of input, you'll need to carry it over manually.

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    Comment #46388013

    You can do it like this, assuming A is the mask of newlines and B is the mask of non-spaces. 1. Compute M1 = ~A & ~B, which is the mask of all spaces that are not newlines 2. Compu…

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    Comment #46387896

    We do this with FreeBSD ports, but users don't have to clone the ports tree unless they want to modify ports or compile them with custom options.

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    Comment #46192202

    And the same reason NVRAM was dead on arrival. No affordable dev systems meant that only enterprise software supported it.

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    Comment #46133815

    That's more "load store architecture" than RISC. And by that measure, S/360 could be considered a RISC.

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    Comment #46133809

    You may enjoy the RISC deprogrammer: https://blog.erratasec.com/2022/10/the-risc-deprogrammer.htm...

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    Comment #46008062

    ARM already has most stuff required for this on board. Two proprietary extensions are used by Rosetta: one emulates the parity (rarely used) and half-carry (obsolete) flags, which …

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    Comment #45881684

    It's very likely that there is some serious autovectorisation going on behind the scenes.

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    Comment #45834171

    Best one was when gedit had the option to syntax highlight for a language named “Los.”

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    Comment #45638676

    Had the same feeling browsing through the Haskell package collection. Felt like and almagamation of PhD theses, none of which were maintained after the author got his degree. Every…

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    Comment #45527403

    I'm talking about how they are able to integrate stuff that normally wouldn't fit into 32 bits (such as 3 operand simd with masking), not about getting the instruction set more com…

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    Comment #45490159

    Also, the VAX instruction encoding is a class of horror above that of x86.

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    Comment #45490134

    ARM64 has a trick up its sleeve: many instructions that would be longer on other architecturea are instead split into easily recognisable pairs on ARM64. This allows for simple inp…

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    Comment #45490094

    LL/SC is performant, it just doesn't scale to high core counts. The VEX encoding is actually only rarely longer than the legacy one, and frequently it is shorter.

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    Comment #45347040

    When I implemented SIMD-accelerated string functions for FreeBSD's libc, I briefly looked at Stringzilla, but the code didn't look particularly interesting or fast. So no surprise …

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    Comment #45300869

    If you give in to an unreasonable person's demands, that person will demand more and more until it all comes crashing down.