Viewing profile — clamchowder

(author here) they try for all instructions, just that it's a prediction w/replay because inevitably some instructions like memory loads are variable latency. It's not like Nvidia …

It does clock ramp from 800 MHz idle to 3.2 GHz under load, with 900, 1000, 1100, 1300, 1500, 1800, 2200, and 2700 MHz steps in between until it hits 3.2 GHz after 71.6 ms. Article…

It was a joke about blurriness. To extend the joke, be glad it doesn't flicker and shimmer. But yes, platforms usually apply compression in terrible ways, and it's especially notic…

Yea Wordpress was a terrible platform and Substack is also a terrible platform. I don't know why every platform wants to take a simple uploaded PNG and apply TAA to it. And don't g…

(author here) When I checked the 7600 XT was much more expensive. Right now it's still $360 on eBay, vs the B580's $250 MSRP, though yeah I guess it's hard to find the B580 in stoc…

Oh that should be fun. Would have to fit it around work though

"don't run any faster than a sequence of simpler instructions" This is false. You can find examples of both x86-64 and aarch64 CPUs that handle indexed addressing with no extra lat…

No, that's not a second level BTB in that regular direct branches don't seem to use it. It's only for predicting indirect branches.

(author here) Just a 32 entry BTB is technically a possibility from microbenchmark results, but the EIC7700X datasheet straight up says: "a branch prediction unit that is composed …

(author here) I compared it to the A75 on the Snapdragon 670, not the 845. I chose that comparison because I have a Pixel 3a (my previous daily driver cell phone), and that's the o…

(author here) by free time and curiosity I mean, I have a day job so I'm able to do this as my hobby

Note - I saw the article through from start to finish. For power measurements I modified my memory bandwidth test to read AMD's core energy status MSR, and modified the instruction…

Yes, I tested on CCD1 (the non-vcache CCD) on both BIOS versions.

Seems like no one ever reads the byline anymore

1. Yeah I agree, both X Elite and many Intel/AMD chips clock well past their efficiency sweet spot at stock. There is a cost to extra pipeline stages, but no one is designing anyth…

1. Performance. Also Arm implemented instruction cache coherency too. Predecode/uop cache are both means to the same end, mitigating decode power. AMD and Intel have used both (tho…

Some notes: 1. Consider M1's 8-wide decoder hit the 5+ GHz clock speeds that Intel Golden Cove's decoder can. More complex logic with more delays is harder to clock up. Of course M…

Oh I don't mind the discussion here at all, I'm just occasionally puzzled at things I thought I was pretty direct about. Honestly though I don't like writing. Finding stuff out abo…

iGPUs like the ones in PHX/MTL have to go into handhelds and ultrabooks, so they're going to be power and thermally limited in before 2-4 MB of cache + LPDDR5 becomes a major bottl…

I simply meant it was ambitious compared to prior Intel iGPUs, especially stuff like Skylake GT2 where you could be playing at 720P low and still not get 30 FPS. The chiplet strate…

4K 120..."There's the bar!" - By ambitious I meant Intel's serious about getting competitive gaming performance in the handheld or thin/light laptop category. MTL's iGPU is ambitio…

(author here) I appreciate the feedback, but I have trouble understanding where you're coming from. "what exactly makes it ambitious?" I thought I outlined that it was much more po…

Well for me it was a matter of how much time it took. I spent enough time understanding the Central Processor with all the weird CDC-specific terms. I had to reread several times b…

I don't know if the CDC 6600 can be considered superscalar. I called it scalar because it can never issue more than one instruction per cycle, and can thus never sustain faster-tha…