Viewing profile — camel-cdr

The create is called portable_simd. There is no reason a portable_simd relu_dot implemention should need to specify the SIMD width. But the design and documentation of portable_sim…

I love how ever example of portable SIMD isn't portable. They specifies a constant SIMD width so it's non-portable. Well, not performance portable, but why are we using SIMD again?…

I tend to search for a few topics with the filter set to past 24 hours and past week. Today that feature seems broken and returns a lot of years old results. Somebody else had a si…

this type of thing usually means you are the product

Well, this explains who has the training data to fake it then.

It used to be $300 for the 8GB RAM version for the first batch in May/June. (16GB for $400)

> So, why not just cover that flaw by adding a carry/overflow flag. Actually, why not just have a single generic 1-bit flag? You could still have cmp + branch, but now you put the …

> Well, cmov is absolutely possible without flags. You see such "select" instructions all the time on GPUs Well, yes, because GPUs need 3r1w anyways, for fmadd, and because a dedic…

Designing an ISA arround carry flags certainly gives you many goodies: cmov, adc, ccmp, larger branch range

That seems like a weird thing to save on, for architectures that have expensive but rarely used things like CLZ on all ALUs. But I hadn't considered the ISA design option of only c…

> Out-of-order pipelines actually have a really elegant way of handling flags, they just store a copy of the flags register on every ROB entry. And yet, flag writing instructions a…

No don't buy this one, it doesn't support RVV. Their newer ones do, but those are a lot more expensive.

> Dart supports RISC-V as a target architecture for compilation, but I'm not really excited about figuring out how to map the wasm-SIMD-style primitives to RISC-V's RVV and so I do…

> No, not really. You can still jump into the middle a 32-bit instruction, and it's possible it can be reinterpreted as a valid 32/16-bit instruction. Remember when people complain…

You can see the encoding limitation it in the design on SVE, which only has destructive operations, but MOVPRFX, which is a round about way of doing 64-bit instructions, without do…

You can benchmark stuff with and without RVC. Once there is faster hardware I want to do such a comparison with a full gentoo build for both sides. However, quantifying what the re…

> E.g. you fetch 66 bytes instead of 64 Not really, you would fetch fewer bytes with RVC [2, page 9], because the code density is better. > I would be really surprised if the lower…

There are two options when designing an ISA to achieve competitive code size, add variable length instructions or add more complex fixed-length instructions which require cracking …

> Yes that's precisely the point of excluding it from the RVA profiles. It would mean that Linux distros don't compile code with C enabled, so chips are free to not support C and t…

\* Fibonacci hashing spreads packed ARGB keys uniformly. Used so that low bits don't dominate the cache. */ return (NSUInteger) ((key * 11400714819323198485ULL) & (NS_COLOR_CACHE_S…

Isn't HTML and CSS already a huge surface to support, unless you are happy with a subset?

> i wish there was just an SDK for building apps (i'll vibe code towards a great epub experience, i'm fine with that) That seems to be what crosspoint-reader is: https://github.com…

I skimmed over the project a bit. It seems quite ambitious to aim to reimplement epub, considering that means supporting HTML, CSS, SVG and JavaScript. Is there a ebook format that…

> unless you're irresponsible enough to connect an LLM to something that actually matters Remember when people said Artifical Intelligence woun't be dangerous, because nobody will …

This is not the correct analogy, because we know that they explicitly used a huge ammount of pirated books and other works.