Viewing profile — bytefire

Main problem with regular (forward-only time) debugging is a state -- memory, CPU, cache etc -- which is contributed to the bug but is completely lost. With time travel debugging t…

It's interesting how little known this exception handling mechanism is: https://stackoverflow.com/questions/51761688/linux-driver-tr...

Thanks. I am actually using this inside a kernel module whose job is to inspect Intel's virtualisation state: https://github.com/bytefire/vmtool

i see, makes sense. may be a different team from V86 worked on it? Conways law :)

good point. may be the central idea of how it's implemented isn't too bad: i see hypervisor as a sort of OS kernel for VMs and the transitions from VM to hypervisor - VM exits - ak…

hi userbinator :) isn't the purpose of virtual 8086 mode somewhat different? i.e. to run real mode applications while the cpu is in protected mode? or did you mean that virtual 808…

very good, thank you. i'll try to tidy it up

very interesting and creative use if EPT, will read the link. thanks for sharing

thank you that means a lot! please do add any information you think is relevant :)

no you didn't overlook. the article doesn't discuss actual mechanics of DRAM init, so thank you for adding this info :) i know there is a process of memory training whose aim is to…

you're right, MRC is a major part of FSP but i think FSP does more work than just initialise memory. it also performs some CPU init and also ICH.

@userbinator thanks for clarification! this is indeed useful and helps understand contradictions.

> The instruction pointer is the IP register. It is zero. it is 0xfff0, at least according to Intel Software Developer's Manual Volume 3, section 9.1.4 "First Instruction Executed"…

this is interesting! i am not aware of how this logic is implemented, i.e. the logic of initial state where 12 most significant bits but thanks for enlightening

@burfog i have updated the post with explanation of how the reset vector address is calculated. thanks for pointing out :)

ah i see your point. here asserted defines a state and not a way of ensuring a certain condition is met (as in higher level languages). yes "initialised to 1" would also convey sam…

sorry could you explain what pinned or fixed mean in this context. by asserted, i mean the corresponding bits being set. similar thing to when one says an interrupt line is asserte…

yes CS not SS. i should fix that. regarding how the CPU addresses 0xffff.fff0 is not exactly specified in the post. actually CS register is loaded with 0xf000 and normally this wou…

yes true. the article deliberately focuses on reset-vector onwards steps. perhaps it should make that clear in the beginning. the ME mention is just to create a context for the sta…