Viewing profile — brucehoult

BASE jumpers and wing suit fliers too.

On my SpacemiT K3 SBC with 32GB RAM (where models run on the eight A100 RISC-V cores with 1024 bit vectors) doing the same task I got 5, 5.8, 6.5 tok/s using gemma-4-26B-A4B-it-QAT…

They have never been annoying to type on a Mac.

I've been posting my writing on the internet since 1990, from a Mac where we all learned how to make en and em dashes, umlauts, accents, degree symbols, proper single and double qu…

Also a user-programmable 300 MHz 8051 (8 bit) primarily there to manage timers and interrupts and wake up the big 64 bit cores. Note that the application-processor 1 GHz C906 and A…

Don't forget the 128 bit vector ISA with 32 registers, supporting up to 64 bit int and FP, and with LMUL=8 you can process 1024 bits with a single instruction (at 3 cycles per 128 …

I've never read any of his economics (didn't know until today that he was one) and formed an opinion based only on his tech press writing. Interesting that he was on the board of T…

Pournelle was good as a kind of (relatively) non-technical user in the early days (70s, early 80s) who just wanted to use computers to write books. Dvorak was quite good, but for m…

We have RISC-V. Software binary compatibility is less important now than it has been for 30 or 40 years of x86 dominance because now we are so over-served by hardware that most sof…

> Why can't anyone build a performant RISC-V cpu? "They" can, and are. Many "they"s. > I'm starting to get the feeling that there is something fundamentally broken in the RISC-V sp…

We have no idea at all what the terms are.

> Finally the chips have to deliver in performance, to actually provide good mobile devices There were still, as recently as 2025, new smartphones being released with only Arm A53 …

> Why not just switch to a slightly different compiler and core, and then you make all your old code safe without verifying it You don't even need a new core. Fil-C makes regular o…

QEMU. Docker, using QEMU under the hood, there automatically with Docker Desktop on Mac & Windows, install QEMU yourself on Linux and configure binfmt_misc to use it.

The THead C906 core is full Linux-capable but is microcontroller-adjacent and has an early draft version of RVV that is different in details but has the same flavour (and at least …

> "arm removing thumb" should have been a strong signal. I don't see any reason to think that Arm ISA designers are any more skilled and knowledgable than RISC-V ISA designers. Giv…

I disagree.

The performance gap between RISC-V and x86 or Arm is in fact closing. The SpacemiT K3 machines which most people who ordered in early May have now received are comparable to the RK…

You can't remove C from future RVA because a large part of the value of RVA is that each version can run all the shrink-wrapped (binary distribution) code built for the previous ve…

Self-evidently, you therefore won't be the person building this machine.

> small cores are arbitrarily given a burden of supporting variable-length instructions Even the smallest commercial microcontroller cores e.g. the CH32V003, support the C extensio…

x86 seems to get by. And how is an instruction spanning a page boundary and causing a page fault any worse than an instruction NOT spanning a page boundary and the next instruction…

The referenced article specifically says $4000, but reading it more carefully now that's the UPGRADE price, not the full price of the machine. Checking also... https://www.macrumor…

They use the GPU but an Apple Silicon GPU has the same high speed access to all the RAM on the machine as the CPU does, rather than having its own walled-off maybe 16 GB VRAM in ma…

A Mac is cheaper than a high end GPU with the same amount of RAM.