Viewing profile — avianes

> I understood it is that a single instruction is executed on a 16-wide SIMD unit, thus processing 16 elements/threads/lanes simultaneously (subject to execution mask of course). T…

> In an operand-collector architecture the threads are still executed in lockstep. > [...] > It is my understanding that you need to synchronize threads when accessing shared memor…

> GPUs are massively parallel devises, they need to keep the scheduler and ALU logic as simple and compact as possible The simplest hardware implementation is not always the more c…

Modern chip designs have an enormous amount of logic and therefore standard-cells. And when you are dealing with a huge amount of cell all together, it quickly becomes unmanageable…

Also, note that: - There is only one Zero (encoded as 0x00), no negative-zero - There is only one NaN (encoded as 0x80)

Are you aware that x86 and ARM/POWER/RISCV memory consistency model are really different? You can encounter very sneaky multitreading bug when running on ARM/POWER/RISCV a program …

Well, first of all, because it shows no results after +10 years. There is definitely no indication that it will work someday. And above all because there are too many choices that …

Not sure what is exactly your thought, since the optimizations you quote don't really takes advantage of any exposed optimization feature of the language. Are your asking why we co…

> unless the compiler devs are working for the same company that makes the CPU Every CPU manufacturing company have a compile team. > This will never work VLIW processors do work, …

You could do unary encoding in a parallel register (and conversely binary encoding using a serial bit stream). The essence of unary encoding is that the number is encoded by the nu…

Building a x86/ARM/RISC-V desktop or server class CPU core is more about the microarchitecture. And RISC-V is an ISA, which is a part of the architecture not the microarchitecture.…

> Separate FP registers - This looks to have started when FPUs were optional and/or physically separate, but that's no longer the case. Using a separate register set for FP is not …

> And again, your intuition about power costs here is just simply wrong. Instruction decode is Simply Not a major part of the power budget of a modern x86 CPU. It's not. I never sa…

> Uh... yes you do? How else do you think it works? No, I literally explain it in my first answer. The part about "1590 decoders" is irrelevant since a misunderstood your message (…

> Um... wat? No CPU tries to decode 99 bytes of memory in a cycle Actually, no x86 processor decodes 8 instructions in parallel. This is an example to illustrate how the number of …

The difficulty is not to decode a single instruction, the difficulty is to decode multiple instructions in parallel (let's say from 5 to 8 instructions in parallel). In a modern hi…

Ok, but then what does the dev do if it fails? It sounds like you want to use the cache as a private local memory near the core, this is called a scratchpad memory. And to maintain…

> why not allow the ISA to query[1] if an L1 access is currently viable (enabling dispatch to different static schedules)? I guess you think of an access that is initiated, with an…

AFAIK C906 is not open-source. The open-source variant of C906 is called OpenC906, and we don't know the eventual difference between C906 and OpenC906.

Another typical use is embedding a public-key in an application or firmware.

> And here's the million dollar idea, to verify you'd need to destructively inspect your chips at EOL to verify you haven't been screwed over. Anyone wants to start a business? it …

> If I'm understanding correctly, this allows us to view (previously obfuscated) code that runs on certain (recent-ish) Intel processors? Yes, but this "code" is the Intel microcod…

> But you’re really getting what the memory controller decides to give you. Yes, here the memory is read through a debug bus. > I could design a memory controller with landmines, a…

> Which machine language is the microcode written in? The mirocode is generally a sequence of uOps. But in Intel's case, there seems to be a more complex mechanism, called XuCode, …