Viewing profile — alexforencich

These things are probably the best bang for your buck right now.

The ex-Alibaba KU3P boards are available for under $200, although you do need a separate JTAG cable with flying leads to load designs on them. I recommend starting with that. I'm b…

This is correct, and the result of those streams has been released as corundum-proto here: https://github.com/fpganinja/taxi/tree/master/src/cndm_proto . Note that this simplified …

I'm using some very cheap (~$200) ex-Alibaba FPGA boards for the initial development of the next-generation version. They have 8 lanes of PCIe gen 3 and two SFP28 capable of operat…

The plan for corundum-ng is to support 400G, but it will be a while before this is available.

The GPU uses https://github.com/alexforencich/verilog-pcie + the Xilinx PCIe hard IP core. When using the device-independent DMA engine, that library supports both Xilinx and Intel…

The GPU uses this: https://github.com/alexforencich/verilog-pcie . And there is an open-source 100G NIC here, including open source 10G/25G MACs: https://github.com/corundum/corund…

It uses https://github.com/alexforencich/verilog-pcie on top of the Xilinx PCIe hard IP core, which provides everything below the transaction layer.

A hammer, perhaps?

https://elixir.bootlin.com/linux/latest/source can be far more helpful than grep for this sort of thing

The graph above that one is totally wrong. The frame overhead graph may be correct, though.

Ah yeah, that's probably true. According to some back of the envelope math, it seems like the distribution should be more like 5%, 1%, 1%, 3%, 50%, 39%, ignoring the first and last…

I think the author may have made a mistake in some of the math. The frame size distribution plots are likely based on the number of frames, not the amount of data contained in said…

Well, we're planning on porting Corundum to the NetFPGA SUME hardware at some point in the near future. Should be relatively straightforward as the PCIe interface on the Virtex 7 i…

Netronome cards are a gigantic PITA to program, and they are not capable of the precise timing that we need.

I don't know where the heck that price came from. The cards are more like $1200 new. https://www.cdw.com/product/exablaze-exanic-x10-network-adap...

We have not done anything like that. Presumably that would be an important thing to do if a commercial product is produced at some point.

That's something we joke about quite a bit in the research group - "back to the future!"

Crosstalk is better than 30 dB, and double pass loss between ports is 5-8 dB. The switch is basically cycling through three or four different interconnection patterns that are defi…

Stradding is an artifact of very wide interfaces. On the Ultrascale+ parts, the PCIe gen 3 x16 interface comes out as a 512 bit wide interface. Every cycle of the 250 MHz PCIe user…

That's part of the research we're doing! Take a look at: https://circuit-switching.sysnet.ucsd.edu/ And: https://arpa-e.energy.gov/sites/default/files/UCSD_Papen_ENL... The current…

No free 40G MAC/PHY. Unfortunately, the Xilinx CMAC is 100G only, and the Xilinx soft 40G MAC/PHY is $$$$. I have looked in to building a 40G/100G switchable MAC/PHY, but it's goin…

There are two hard things in computer science: cache invalidation, naming things, and off-by- one errors.

Yes, I am aware of those. However, the kintex PCIe interface is a bit of a pain as it has a TLP straddling mode that can't be disabled, so it will be some time before it's supporte…

It depends on the programming interface. JTAG is bit serial and rather slow, so it can take quite a while to load a large FPGA via JTAG. However, there are several other interfaces…