Viewing profile — aengelke

I'm a bit late, but: Umbra doesn't use AsmJIT anymore since many years, it was too slow.

That's not generally correct. Compile-time is a concern for several databases.

> It's very difficult to do low-latency queries if you cannot cache the compiled code This is not too difficult, it just requires a different execution style. Salesforce's Hyper fo…

> What's the rationale? Gift cards are used by phishers. In our institution, we routinely get personalized spam mails (in the name of the corresponding group lead of the recipient,…

I fully agree, but: > these are the string instructions like REP MOVSB AArch64 nowadays has somewhat similar CPY* and SET* instructions. Does that make AArch64 CISC? :-) (Maybe REP…

> LEA happens to be the unique instruction where the memory operand is not dereferenced Not quite unique: the now-deprecated Intel MPX instructions had similar semantics, e.g. BNDC…

Been there, done that during my PhD (code: [1]). Works reasonably well, except for compile times (for which I implemented a caching strategy). However, due to calling conventions, …

Actually, nowadays Arm describes the ISA as a load-store architecture. The RISC vs. CISC debate is, in my opinion, pretty pointless nowadays and I'd prefer if we'd just stop using …

The same site hosts [1], but that's not nearly as nice as the 32-bit version. It's also a bit outdated. [1]: https://www-user.tu-chemnitz.de/~heha/hs/chm/x86.chm/x64.htm

> I’d suggest starting with arm I agree: AArch64 is a nice instruction set to learn. (Source: I taught ARMv7, AArch64, x86-64 to first-year students in the past.) > how simple inst…

TPDE co-author here. Nice work, this was easier than expected; so we'll have better upstream ORC support soon [1]. The benchmark is suboptimal in multiple ways: - Multi-threading m…

> but typically a change to the preprocessed output implies a change to the IR (e.g., it's a functional change and not just a variable name change or something). Otherwise, why wou…

Or rather: There are 2 hard problems in computer science: cache invalidation, naming things, and off-by-1 errors. (source: https://martinfowler.com/bliki/TwoHardThings.html )

Template instantiation caching is likely to help -- in an unoptimized LLVM build, I found that 40-50% of the compiled code at object file level is discarded at link-time as redunda…

In AoT compilation, unoptimized code is primarily useful for debugging and short compile-test round trips. Your point on C++ is correct, but test workloads are typically small so t…

The paper is rather selective about the used benchmarks and baselines. They do two comparisons (3 microbenchmarks and a re-implementation of a few (rather simple) database queries)…

There's a longer paragraph on that topic in Section 8. We also previously built an LLVM back-end using that approach [1]. While that approach leads to even faster compilation, run-…

In terms of runtime performance, the TPDE-generated code is comparable with and sometimes a bit faster than LLVM -O0. I agree that front-ends are a big performance problem and both…

The documentation has a list of currently unsupported features: https://docs.tpde.org/tpde-llvm-main.html

Storing the string length explicitly as an 8-byte integer does have a measurable cost. Consider llvm::Twine as an example, it supports storing a null-terminated string and a ptr+le…

It's probably worth noting that TySan currently only catches aliasing violations that LLVM would be able to exploit. For some types, e.g. unions, Clang doesn't emit accurate type-b…

These are tests that use some more LLVM tools (llvm-objdump, llvm-dwarfdump, not). Could you try after building these tools in addition to FileCheck? Do the TPDE-LLVM tests, which …

> Also there are processors with larger vector length How do these fare in terms of absolute performance? The NEC TSUBASA is not a CPU. > Do you have more examples of this? I porte…

Thanks, I misremembered. However, the microarchitecture is a bit "weird" (really HPC-targeted), with very long latencies (e.g., ADD (vector) 4 cycles, FADD (vector) 9 cycles). I re…

> if we didn't settle on executing compiled machine code exactly as-is, and had a instruction-updating pass (less involved than a full VM byte code compilation) Apple tried somethi…