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The neoTRNG provides a tiny (less than 70 LUTs) true random number generator for any FPGA. No device-specifc macros, libraries or attributes are used at all. The quality of the gen…

This is a tiny (less than 200 LUTs) Physical Unclonable Function hardware module for FPGAs. It provides a unique 96-bit "fingerprint" that can be used for security-related applicat…

You cannot really maintain that. The controller has to adapt. That is what the two reset signals are for. The synchronous one can be trigger by application logic (for example some …

The core provides (depending on configuration) ~0.9 coremarks per MHz. The base core has 32 GPIOs (32xinput + 32xoutput) and no DMA. If you need a DMA or more GPIOs you can attach …

I thought so, too. I have read about the Lattice MACH-NX having a secure enclave based on a RISC-V CPU, but it seems like this is just a soft-core CPU as well.

It is hard to compare two RISC-V cores if they do not have similar configuration options. For example: what kind of ISA extensions, supported traps, custom extensions, CSRs, etc. d…

Full-scale RISC-V soft-core microcontroller SoC with on-chip debugger compatible to openocd and GNU gdb

A size-optimized and highly customizable soft-core micorcontroller based on a rv32[i/e][m][a][c][b][Zfinx][Zicsr][Zifencei] +[u][PMP][HPM] CPU. The SoC includes internal memories/c…