Viewing profile — _chris_

Longer time horizon -- mortage inflates away. In the short-term, only need to beat the property tax bill, especially if the interest rate is <3% and the property is increasing in v…

A BPU needs to predict 3 things: - 1) Is there a branch here? - 2) If so, is it taken? - 3) If so, where to? If a conditional branch is never taken, then it's effectively a NOP, an…

> A lot of the time this is a hint to the compiler on what the expected paths are so it can keep those paths linear. IIRC, this mainly helps instruction cache locality. The real va…

> The thing holding back VLIW was compilers were too dumb That’s not really the problem. The real issue is that VLIW requires branches to be strongly biased, statically, so a compi…

Wouldn’t a smart tv do something ... smarter than just using the default dns given to it by the network? I’m not up to speed on this stuff but I thought pihole only blocked the sim…

It’s not that hard to debug— your signal names and register names all carry through. Sure, lots of temp wires get generated but that’s never where your bug is.

> allow to select the purchase price within the last 2 years I don't think that's true. My reading of that is "you lock in the price on your start date and can keep that for the ne…

> I’d be interested in understanding why the compilers never panned out but have never seen a good writeup on that. Or why people thought the compilers would be able to succeed in …

> L1i matters, people! RISC-V consistently wins on L1i footprint. The complaining is about number of dynamic instructions ("path length"), which can hit you if you don't fuse. Of c…

> > Cascade discovered 4 bugs in BOOM and CVA6 that produce wrong output val- ues regardless of the microarchitectural state > These are unacceptable bugs, showing a lack of archit…

Looks like from Appendix D that only 2 bugs were found in BOOM: > 1. Inaccurate instruction count when minstret is written by software I don't know what that means, but having mins…

If you want to do some further archeology, check out the SMIPS ISA, which I believe dates back to 2005 (which itself gradually evolved from the T0/Scale/6.371 MIPS ISAs; and the ea…

I also get a permission error: but I think this ( https://inst.eecs.berkeley.edu/~cs250/fa10/handouts/lab2-ris... ) is the same file, and functionally the same as the fa11 version?…

To add to this, Andrew et. al. at Berkeley built SPARC cores, so they were well aware of what it took to implement hardware to run SPARC software. I believe some of the really anno…

I believe early on there was a change to a pre-AUIPC instruction due to potential infringement fears (for PC-relative indexing); but everything else was understood to be following …

And adds non-destructive instructions. > "In addition, legacy integer instructions now can also use EVEX to encode a dedicated destination register operand – turning them into thre…

> their clean orthogonal instruction encoding is so inefficient (e.g. it wastes a lot of instruction cache) Perhaps, although ARMv8 is fixed 4 bytes and x86-64 averages more than 4…

Custom opcodes have a protected spot in the opcode map; but there's nothing that prevents two different CPUs from using the same custom opcode pattern to mean two different instruc…

Very different. RISC-V's vectors (RVV) are "variable length", so the programmer can request a length and the machine tells you what it can give you. Different machine versions can …

> They said "5 stage", which sounds to me like no out-of-order fancy stuff of the sort we've been used to. That's inefficient for an FPGA softcore; wires are too expensive, CAMs ar…

> I wonder if we're ever going to see a 8wide decoder RISC-V. Considering there are 6-wide x86 cores on the market, I wouldn't be too concerned about RISC-V going wide. The instruc…

Lying all the time has consequences.