Viewing profile — WillFlux

Thanks. I want to keep the software simple while having proper support for the graphics and audio hardware. I already have some prototype software written is RISC-V asm. I’ll proba…

I'm surprised by this. 1280x768 is an unusual resolution, what display timings are you using? I've found 1024x768 and 1280x720 are both well supported. I tend to use these display …

Hello, I'm the author of the Project F blog. I'd be happy to field any questions you have.

RISC-V takes a different approach to branching, even compared to other RISC processors. There are no status registers AKA condition codes.

Load-store architecture is a defining quality of RISC in general and RISC-V in particular. If you're used to a rich set of addressing modes in x86 or 68K, coding on RISC-V asm is a…

Burrell Smith and Andy Hertzfeld worked for Radius on the Full Page Display. How different would Apple have been if it had held onto more of the original Macintosh team in the mid-…

68000 is, in many ways, the pinnacle of assembler for programming, but RISC-V is pretty fun, too. I hope RISC-V tempts a few more people to try asm programming (again).

Intel might not even be making another generation of discrete consumer GPUs. See the numerous stories in the tech press over the last few months. We have to hope AMD has the price,…

Thank you. I can't promise to get to the new design until early 2023 as I have many hardware designs I want to finish this year. Once you've got a design working in Verilator, I st…

If you'd link to a screenshot of what you see, that would be helpful. I have noticed the font renders thinner on Windows. I plan to look at the design over the winter: some things …

Oh, I’ll get to that :D

The examples aren’t limited to VGA; I support four different outputs with these designs. * VGA using a Pmod board (you could also create your own register ladder) * DVI using the T…

Even if you don’t have an FPGA, you can run these hardware designs on your PC with SDL and Verilator. It’s really simple to set up: https://projectf.io/posts/verilog-sim-verilator-…