Viewing profile — VioletVillain
VioletVillain
HN member- Joined
- Sun, Jan 05, 2020, 12:59 PM UTC
- HN karma
- 12
- Public activity
- 12 items
- HN profile
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About VioletVillain
https://github.com/Thraetaona
Recent public activity
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Comment #41092192
For the posterity, I've managed to make Blitzping much faster: on the ARMv8-A device, it went from ~10.5 MiB/s to ~120 MiB/s. Instead of sendto(), I used a single connect() call to…
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Comment #40991722
Thanks, that might be exactly what I am looking for; I'll check it out.
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Comment #40991696
As of now, the code is just a proof of concept for achieving higher throughput than what currently available tools (e.g., nping/hping3) are capable of. Other than that, nping is ju…
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Comment #40991647
Those underpowered processors were only used as an optimization benchmark; if it runs good enough there, you could always throw more computational power and cores at it. EDIT: Also…
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Comment #40971224
Thanks, I hope it'll be useful in your experiments. As for looking more realistic, I think it does the job; when I checked with Wireshark checked how different applications (e.g., …
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Show HN: Blitzping – A far faster nping/hping3 SYN-flood alternative with CIDR
I found hping3 and nmap's nping to be far too slow in terms of sending individual, bare-minimum (40-byte) TCP SYN packets; other than inefficient socket I/O, they were also attempt…
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Comment #40583688
[flagged]
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Show HN: An efficient SRL32 (cascading shift registers) clock prescaler in VHDL
Having just started learning FPGA Hardware Description Languages by attempting to write a simple LED blinker, I found that the overwhelming majority of the Internet's solution to s…
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Comment #23567695
Hello! Author here. First I should mention that the project is opensource, available here: https://github.com/VioletVillain/EXACT For convenience I'll also include a basic overview…
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