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TanjB

HN member
Joined
Sat, Apr 04, 2020, 6:30 PM UTC
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123
Public activity
13 items

About TanjB

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Recent public activity

  1. comment
    Comment #40754437

    No, this is panels from which interposers will be made. Which are now larger than chips and rectangular, so wasted edges from a 300mm wafer are high. The proposed size is much larg…

  2. comment
    Comment #38001251

    MIPS had load const to high or low half. More that 40 years ago Transputer had shift-and-load 8 bit constants. Lots of ancient precedents for rare big constants.

  3. comment
    Comment #38001148

    Interesting idea. Effectively moving the extra decode stage in front of the Icache, making the Icache a bit like a CISC trace/microOp cache. On a 512b line you would add 32 bits to…

  4. comment
    Comment #36006939

    When Moore wrote in 1965, commercial use of MOS was 10 years in the future and Dennard scaling would not become widely understood and stirring interest in CMOS until 15 years in th…

  5. comment
    Comment #35890876

    DRAM is not greatly affected by radiation, because the capacitors are large structures relative to radiation events. SRAM is affected, which is why SRAM arrays should always use SE…

  6. comment
    Comment #33994967

    Those cell sizes are theoretical anyway. They do exist, but on sample chips optimized for SRAM. If you design a chip and select an IP macro for SRAM the density you actually get ma…

  7. comment
    Comment #32800442

    Nice idea, but I honestly don't think it has much value for study. It was a solution to a problem which is no longer important, and what impressed David (and was fun for me) was im…

  8. comment
    Comment #32800323

    TeX was beautiful. Both the algorithms (it was a masterwork on typesetting, still a good reference for anyone doing text layout) and the book.

  9. comment
    Comment #32800304

    Hi David, thanks for the kind words. I still have the source for that I think, it was written around 1984 originally for a project of my own, then sold to Logitech, Zorland, and Bo…

  10. comment
    Comment #28611743

    Memory fail. No ECC, uses DDR4 instead of LPDDR4x (which has a 1-bit ECC and superior bandwidth) which the Tiger Lake CPUs would support.

  11. comment
    Comment #27689987

    Apple is probably paying closer to $20k per wafer, including test and packaging. There have been leaks on pricing in the industry, leading edge process is expensive. Even at 50M ch…

  12. comment
    Comment #27564255

    Ironic. CMP was developed and perfected at IBM, who used it to make complex low volume products. Excellent insight. CMP and damascene metal (guess who!) really kicked CMOS into top…

  13. comment
    Comment #22780336

    Some of the issues in the original paper are real (except the hologram where they have transformed marketing hype for stereo images into a real expectation of transmitting hologram…