Viewing profile — Remnant44
Remnant44
HN member- Joined
- Fri, Apr 25, 2014, 8:21 PM UTC
- HN karma
- 552
- Public activity
- 153 items
- HN profile
- View on Hacker News ↗
About Remnant44
No profile information was provided.
Recent public activity
-
comment
Comment #49247168
This was an unexpected find on HN but I found it very moving. Good writing lets you do something that is almost impossible otherwise; to get a glimpse inside someone else's mind an…
-
comment
Comment #49193984
I haven't had a chance to dig into the repo at all, so that's excellent, thank you!
-
comment
Comment #49193320
Looks very promising - I've been looking for a good delaunay library that supports constrained delaunay. It looks like their performance benchmark is including multithreading, whic…
-
comment
Comment #48663429
Do you have any sources for this? I have also heard of rabbit starvation many times over the years, and it has always been in the context of too taking in too little fat -- essenti…
-
comment
Comment #48427279
I agree with you, but also: outside of anything else, amdahls law means that as the parallel performance grows, we become _more_ limited by the inherently serial code, and thus sin…
-
comment
Comment #48171568
It's a little dramatic to say avx512 is dead versus 10 - rather, I would say that avx10 finalizes a universally available set of avx512 extensions. For AVX 10.1, there's essentiall…
-
comment
Comment #47199580
There's a whole lot of us out there. I don't know if there's still a future in the thing that I love, which is where all the malaise comes from.
-
comment
Comment #46843471
I love me some isa extension, I'd love to know what these are intended and useful for for though. 1 bit inference? I hear they could be useful in crypto as well, but that's out of …
-
comment
Comment #46712268
While you may be correct in the sense that, in a public acquisition statement, people should be inferring enormous context and not taking anything said at face value. It's simultan…
-
comment
Comment #46683059
Fort what it's worth, I had the exact same experience you did when I started writing SIMD code explicitly with intrinsics. I avoided it for a long time because, well, it was so dam…
-
comment
Comment #46682856
AVX doesn't require alignment of any memory operands, with the exception of the specific load aligned instruction. So you/the compiler are free to use the reg,mem form interchangib…
-
comment
Comment #46675870
There are many situations where your data is essentially _majority_ unaligned. Considerable effort by the hardware guys has gone into making that situation work well. A great examp…
-
comment
Comment #46675181
which honestly, shouldn't be neccessary today with avx512. There's essentially no reason to prefer the aligned load/store commands over the unaligned ones - if the actual pointer i…
-
comment
Comment #45833049
In practical use for simd, various min/max operations. On Intel at least, they propagate nan or not based on operand order
-
comment
Comment #45638826
I've run into this as well. Problem is that linear RGB is most definitely not a perceptually uniform space, so blending in it frequently does something different than you want. Use…
-
comment
Comment #45596675
Essentially ever other use case for a computer. Whether you're playing games, or editing videos, or doing 3D work, or trying to digest the latest bloated react mess on some website…
-
comment
Comment #45556658
I've had just the smallest touch of this caring for my elderly parents, and you have my deep empathy. It's exhausting and really really hard.
-
comment
Comment #45521710
totally - especially given how bandwidth constrained CPUs still are, going wider than 512 doesn't make much sense. 512 itself was a stretch for quite a long time (and all the negat…
-
comment
Comment #45521529
Sure.. in detail and abstracted slightly, the byte table problem: Maybe you're remapping RGB values [0..255] with a tone curve in graphics, or doing a mapping lookup of IDs to inde…
-
comment
Comment #45519965
Yes and no. I think neon is undersized for today at 128bit registers -- if you're working with doubles for example, that's only two values per register, which is pretty anemic. Thi…
-
comment
Comment #45519829
I'm just happy that finally, with the popularity of zen4 and 5 chips, AVX512 is around ~20% of the running hardware in the steam hardware survey. It's going to be a long while befo…
-
comment
Comment #45440586
I think the most interesting thing here is the near-lack of NUMA effects on memory access, giving fairly easy to achieve high bandwidth memory. Combined with the double-width fabri…
-
comment
Comment #45023500
For sure.. for what it's worth though, I have run across several references to arm also implementing uop caches as a power optimization versus just running the decoders, so I'm inc…
-
comment
Comment #45023472
I was going to mention this as well. Source: chipsandcheese.com memory latency graphs
-
comment
Comment #45020647
ARM instructions are fixed size, while x86 are variable. This makes a wide decoder fairly trivial for ARM, while it is complex and difficult for x86. However, this doesn't really h…