Viewing profile — MootWoop

Sounds great! I'll do my best to answer all questions :-) My email is matthieu.wipliez@synflow.com

Matthieu, co-founder of Synflow here. Maybe I could help? Don't hesitate to send me an email!

Yep, I'm Matthieu! You can send me an email at matthieu.wipliez at synflow.com

> Today's beginners don't make the tools. Not necessarily, I am a beginner in hardware design, and I am creating a new programming language and IDE for hardware design. > The acade…

Good point about the reasons of productivity leaps. Funnily enough, I recall that one of the main selling points of Java was portability (the famous "Write Once Run Everywhere"), e…

To whomever downvoted this: would you mind telling me why? Have I offended you in some way? Is it because of the criticism of the hardware industry? Or the sarcasm?

2. I am curious to hear what you think about our solution of wrapping existing VHDL/Verilog in an external task in Cx? http://cx-lang.org/documentation/tasks#external

> The bugs are not due to language generally. That's like saying that buffer overflows are not due to how strings are represented in C. Yes a bug is the programmer's fault, but lan…

> For an engineer it does not matter about the language that describes the circuit. [...] Typing it in is the easiest part. Well... once upon a time, people were writing software w…

> it looked very promising Thanks! > Reading from a port twice seems to trigger a clock cycle (did I get that right?) You did! It is by design that reading from the same port twice…

That's the beauty (and sometimes the curse) of hardware design: it doesn't need a processor to run. You essentially describe an electronic circuit, and "program" (configure would b…

Interesting, I feel like you would like what we've done with the Cx language at Synflow. Probably the exact opposite of CλaSH, the language is sequential imperative (C-like even) a…

Hard to say, it depends on what you consider better. It certainly is more concise than the equivalent Verilog (just like Haskell is more concise than pretty much any language I kno…

The way I see it, it's Register Transfer Level, just written differently. Instead of writing: @always(clock) counter you write: counter = s where s = register 0 (s + 1) per http://…

How well HLS does highly depends on the source code (this is in general and not specific to Vivado HLS). If your code is a simple loop over an array and you add a vendor-specific #…

@gothenburg @mng2 I get that you think it's not useful or even it's crazy, especially as both of you seem to be seasoned hardware designers. But as a software guy myself, there's n…

Really? Aren't they using VHDL generics/Verilog parameters? Cx supports specialization of entities with this kind of semantics, so you give an instance parameters and the compiler …

Yes it is still in use, and the simulation capabilities are quite advanced! It remains a HDL, better than VHDL and Verilog, so you still have to worry about resetting, clocks and s…

That's a very good point. In fact the main difference in semantics is that Cx code is structured. Sure in VHDL/Verilog you have functions and if statements and loops. But they can …

Exactly! Isn't that a breeze? Reset and clock are implicit by default, but you can always override them (change name, set reset synchronous, etc.)

Don't worry, you're not the first to find that this looks similar to Verilog. I have commented about the syntax aspect on EETimes: see http://www.eetimes.com/author.asp?section_id=…

Good point, we need to make this clearer I think. We (Synflow) have a compiler and IDE that you can download from https://www.synflow.com The compiler and IDE are open source, and …

We hope so too :) If somehow Cx doesn't live up to its promises and what you expect from it, please let us know! We're still improving it based on the feedback we get. Thanks!