Viewing profile — Dolu

> The HLS generated verilog is name mangled Chisel, SpinalHDL, Clash, Migen, Amaranth aren't HLS Most of the time, if you get some verilog out of those tools with mangled names, it…

> FWIW, that's not true, you can write it as one: While technicaly you are right, i think you missed the spirit of what the doc was saying. You may write it all in a single process…

On this talk : - https://youtu.be/f-b4QOzMyfU?t=300 - https://youtu.be/f-b4QOzMyfU?t=492 => yes and no The industry lack's of wide profiles (hardware engineer with good software un…

Checkout SpinalHDL it keep much more of your hardware description semantic inside the generated Verilog

Wrong, it was implemented from scratch. Look the same, but was implemented in a very different philosophy. SpinalHDL is from my opinion much better.

I was exactly in the same mood some years ago, until i triey one of those HDL alternative.

Honnestly, i haven't realy think about it. Not a constraining one, but more something like : Do what ever you want with it, but if you find a bug, please tell me, and if you use it…

Cached an uncached memory access are currently staticaly specified by range : https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/s... From 0xF000000 to 0xFFFFFFFF access wi…

Yes it would be, it is very easy to retarget the CPU to another memory bus. Then the Wishbone one isn't "perfect" as it can't map memories which have latencies without performance …

Yes i agree, would have been more convenent to use the integrated jtag of the FPGA, but i focused on making an universal solution first :)

Are you sure it need a license ? I were thinking that AXI usage is royalities free ( https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_A... )

They aren't made for external com

Yes a standard would be great, with all the feature provide by those embedded HDL, but i'm realy not sure the industry could make it. #systemverilog

Yes kind of, SpinalHDL is a from scratch fork

Yes, silicon implementation provide the JTAG, but it's very likely their implementation will not be reusable for FPGA project (including JTAG debug things) because of their over co…