Viewing profile — ChrisKjellqvist

I've been using HLS recently and from my understanding, all you need is `v++`. [link to example HLS makefile]( https://github.com/Xilinx/Vitis_Accel_Examples/blob/f61637e9... )

I think the problem with such an architecture is that latency isn't a limit on timing closure from a hardware sense now, but you still have to consider it now from the software com…