Viewing profile — BrannonB

Your second point was that HW engineers haven’t learned about sharing—as evidenced by the fact that they use a different term for it than SW does. Again this is evaluating HW throu…

25 years of high performance chip design. Perhaps you’re an FPGA guy? The tradeoffs are different in that world.

If you think Verilog is bad, you should see the languages used by heart surgeons, civil engineers and rocket scientists. The language of human biology is ridiculously verbose witho…