Viewing profile — Andrey_Filippov

We do it now with thermal images: https://image-ppubs.uspto.gov/dirsearch-public/print/downloa...

A focus puller is already built using FPGA+GNU/Linux - https://github.com/Qinematiq

I think Obama should not just pardon Snowden, but nominate him to a position of NSA director. Snowden is both a top professional and cares about our rights and freedoms. NSA is sti…

Yes, I'm guilty in DRY violation and I mentioned it in the post - I still manually translate Verilog to Python when go from simulation/debugging to hardware testing/debugging. And …

Yes, you are absolutely right about "repeatedly solved problems", so it is definitly one in the series of "yet another ...". I'll try your program on our project files to see what …

Scott, you are right, and I try to do it that way (there are many registers in the design with "_ram" suffix. But I did have some problems when Vivado incorrectly inferred small no…

Thank you, at leas one of "these people" got it. Interesting project, but again - it is still far performance-wise. We really appreciate work of developers of the Free Software too…

What objections do you have to the requirements to release documentation? Similar anti-monopoly laws already exist in other areas. It would make Clifford's job much easier (so you …

No single dominating block. Camera has 4 sensor channels (now either 12 bit parallel or Aptina HiSPI) with gamma and histograms, 16-channel DDR3 controller, 4 compressor channels, …

Project uses 84% of Zynq (7030), it will not fit in Lattice :-(

Not really many are "analog" and we already have GTX model. Some primitives are just buffers, some - memories (block RAM), one PLL. I do not think it is a "rocket science" to creat…